Drive method of el display apparatus

ABSTRACT

To provide a drive method capable of maintaining gradation display performance regardless of screen display brightness.  
     Reference numeral  491 R denotes a regulator used to control reference current for red (R). By adjusting a reference current for R linearly, it is possible to linearly vary a current flowing through a transistor  472   a  which constitutes a current mirror with a transistor  471 R. This changes a current flowing through a transistor  472   b  which has received a current-based delivery from the transistor  472   a  in a transistor group  521   a . This in turn causes changes to a transistor  473   a  in a transistor group  521   b  which constitutes a current mirror with the transistor  472   b , resulting in changes to a transistor  473   b  which has received a current-based delivery from the transistor  473   a . Thus, since drive current of the unit transistor  484  changes, programming current can be changed linearly. Reference numeral  491 G denotes a regulator used to control reference current for green (G) and reference numeral  491 B denotes a regulator used to control reference current for blue (B).  
     By adjusting  491 R,  491 G, and  491 B, it is possible to adjust white balance easily and change screen brightness easily. Besides, gradation display performance is maintained at any screen brightness.

TECHNICAL FIELD

The present invention relates to a self-luminous display panel such asan EL display panel which employs organic or inorganicelectroluminescent (EL) elements as well as to a drive circuit (IC) forthe display panel. Also, it relates to an information display apparatusand the like which employ the EL display panel, a drive method for theEL display panel, and the drive circuit for the EL display panel.

BACKGROUND ART

Generally, active-matrix display apparatus display images by arranging alarge number of pixels in a matrix and controlling the light intensityof each pixel according to a video signal. For example, if liquidcrystals are used as an electrochemical substance, the transmittance ofeach pixel changes according to a voltage written into the pixel. Withactive-matrix display apparatus which employ an organicelectroluminescent (EL) material as an electrochemical substance,emission brightness changes according to current written into pixels.

In a liquid crystal display panel, each pixel works as a shutter, andimages are displayed as a backlight is blocked off and revealed by thepixels or shutters. An organic EL display panel is of a self-luminoustype in which each pixel has a light-emitting element. Consequently,organic EL display panels have the advantages of being more viewablethan liquid crystal display panels, requiring no backlighting, havinghigh response speed, etc.

Brightness of each light-emitting element (pixel) in an organic ELdisplay panel is controlled by an amount of current. That is, organic ELdisplay panels differ greatly from liquid crystal display panels in thatlight-emitting elements are driven or controlled by current.

A construction of organic EL display panels can be either asimple-matrix type or active-matrix type. It is difficult to implement alarge high-resolution display panel of the former type although theformer type is simple in structure and inexpensive. The latter typeallows a large high-resolution display panel to be implemented, butinvolves a problem that it is a technically difficult control method andis relatively expensive. Currently, active-matrix type display panelsare developed intensively. In the active-matrix type display panel,current flowing through the light-emitting elements provided in eachpixel is controlled by thin-film transistors (transistors) installed inthe pixels.

Such an organic EL display panel of an active-matrix type is disclosedin Japanese Patent Laid-Open No. 8-234683. An equivalent circuit for onepixel of the display panel is shown in FIG. 46. A pixel 16 consists ofan EL element 15 which is a light-emitting element, a first transistor11 a, a second transistor 11 b, and a storage capacitance 19. Thelight-emitting element 15 is an organic electroluminescent (EL) element.According to the present invention, the transistor 11 a which supplies(controls) current to the EL element 15 is referred to as a drivertransistor 11. A transistor, such as the transistor 11 b shown in FIG.46, which operates as a switch is referred to as a switching transistor11.

The organic EL element 15, in many cases, may be referred to as an OLED(organic light-emitting diode) because of its rectification. In FIG. 46or the like, a diode symbol is used for the lgiht-emitting element 15.

Incidentally, the light-emitting element 15 according to the presentinvention is not limited to an OLED. It may be of any type as long asits brightness is controlled by the amount of current flowing throughthe element 15. Examples include an inorganic EL element, a whitelight-emitting diode consisting of a semiconductor, atypicallight-emitting diode, and a light-emitting transistor. Rectification isnot necessarily required of the light-emitting element 15. Bidirectionaldiodes are also available. The EL element 15 according to the presentinvention may be any of the above elements.

In the example of FIG. 46, a source terminal (S) of the P-channeltransistor 11 a is designated as Vdd (power supply potential) and acathode of the EL element 15 is connected to ground potential (Vk). Onthe other hand, an anode is connected to a drain terminal (D) of thetransistor 11 b. Besides, a gate terminal of the P-channel transistor 11a is connected to a gate signal line 17 a, a source terminal isconnected to a source signal line 18, and a drain terminal is connectedto the storage capacitance 19 and a gate terminal (G) of the P-channeltransistor 11 a.

To drive the pixel 16, a video signal which represents brightnessinformation is first applied to the source signal line 18 with the gatesignal line 17 a selected. Then, the transistor 11 a conducts, thestorage capacitance 19 is charged or discharged, and gate potential ofthe transistor 11 b matches the potential of the video signal. When thegate signal line 17 a is deselected, the transistor 11 a is turned offand the transistor 11 b is cut off electrically from the source signalline 18. However, the gate potential of the transistor 11 a ismaintained stably by the storage capacitance (capacitor) 19. Currentdelivered to the EL element 15 via the transistor 11 a depends ongate-source voltage Vgs of the transistor 11 a and the EL element 15continues to emit light at an intensity which corresponds to the amountof current supplied via the transistor 11 a.

Incidentally, the entire disclosure of the above document isincorporated herein in its entirety.

Since liquid crystal display panels are not self-luminous devices, thereis a problem that they cannot display images without backlighting. Also,there has been a problem that a certain thickness is required to providea backlight, which makes the display panel thicker. Besides, to displaycolors on a liquid crystal display panel, color filters must be used.Therefore, there has been a problem of the lowered usability of light.Also, there has been the problem of narrow color reproduction range.

Organic EL display panels are made of low-temperature polysilicontransistor arrays. However, since organic EL elements use current toemit light, there has been a problem that variations in thecharacteristics of the transistors will cause display irregularities.

The display irregularities can be reduced using current programming ofpixels. For current programming, a current-driven driver circuit isrequired. However, with a current-driven driver circuit, variations willalso occur in transistor elements which compose a current output stage.This in turn causes variations in gradation output currents from outputterminals, making it impossible to display images properly.

DISCLOSURE OF THE INVENTION

To achieve this object, a driver circuit for an EL display panel (ELdisplay apparatus) according to the present invention comprises aplurality of transistors which output unit currents and produces anoutput current by varying the number of transistors. Also, the drivercircuit is characterized by comprising a multi-stage current mirrorcircuit. A transistor group which delivers signals via voltages isformed densely. Also, signals are delivered between the transistor groupand current mirror circuit group via currents. Besides, referencecurrents are produced by a plurality of transistors.

A first invention of the present invention is a drive method of an ELdisplay apparatus that comprises a switching element which turns on andoff a current path between a driver transistor and an EL element, ineach pixel, characterized in that the drive method comprises the stepsof:

-   -   aggregating image data or data equivalent to image data; and    -   turning off the switching element for a longer period if the        aggregated data is large in amount than if the aggregated data        is small in amount.

A second invention of the present invention is an EL display apparatuscomprising:

-   -   a display panel in which EL elements are formed in a matrix; and    -   a source driver circuit which supplies programming current to        the display panel,    -   characterized in that the source driver circuit comprises an        output stage which has a plurality of unit current elements and        a variable circuit which controls current flowing from the unit        current elements.

A third invention of the present invention is a drive method of an ELdisplay apparatus that comprises a moving-picture detection circuitwhich detects moving pictures and a feature extraction circuit whichextracts features of video images, characterized in that the drivemethod of the EL display apparatus implements:

-   -   a first operation of changing the number of selected pixel rows        depending on output data from the moving-picture detection        circuit; and    -   a second operation of changing the number of selected pixel rows        depending on output data from the feature extraction circuit.

A fourth invention of the present invention is an EL display apparatuswhich controls brightness of a screen using a ratio between non-displayand display areas on the screen, characterized in that the EL displayapparatus comprises:

-   -   the display area in which EL elements and driver transistors        that drive the EL elements are formed in a matrix;    -   gate signal lines which transmit voltages that turn on and off        the EL elements in each pixel row;    -   a gate driver circuit which drives the gate signal lines;    -   an aggregation circuit which aggregates image data or data        equivalent to image data; and    -   a conversion circuit which converts aggregation results produced        by the aggregation circuit into a start pulse signal for the        gate driver circuit.

A fifth invention of the present invention is a control method of an ELdisplay apparatus which controls brightness of a screen using a ratiobetween non-display and display areas on the screen, characterized bygenerating a delay time when changing the ratio between the non-displayand display areas on the screen from a first ratio to a second ratio.

A sixth invention of the present invention is the drive method of an ELdisplay apparatus according to the fifth invention of the presentinvention, characterized in that the display area/(the non-displayarea+the display area on the screen) is from 1/16 to 1/1 both inclusive.

A seventh invention of the present invention is an EL display apparatuscomprising:

-   -   a display panel in which each pixel contains a capacitor, an EL        element, and a P-channel driver transistor which supplies        current to the EL element and pixels are arranged in a matrix;        and    -   a source driver circuit which supplies programming current to        the display panel,    -   characterized in that the source driver circuit comprises an        output stage which has an N-channel unit transistor that outputs        a plurality of unit currents.

An eighth invention of the present invention is the EL display apparatusaccording to the seventh invention of the present invention,characterized in that if capacitance of a capacitor is Cs (pF) and onepixel occupies an area of S (square μm), a condition 500/S≦Cs≦20000/S issatisfied.

A ninth invention of the present invention is the EL display apparatusaccording to the seventh invention of the present invention,characterized in that if pixel size is A (square mm) and predeterminedwhite raster display brightness is B (nt), where the programming currentI (μA) from the source driver circuit satisfies a condition(A×B)/20≦I≦(A×B).

A tenth invention of the present invention is the EL display apparatusaccording to the seventh invention of the present invention,characterized in that if the number of gradations is K and size of theunit transistor is S t(square μm), conditions 40≦K/{square root}{squareroot over ( )}(St) and St≦300 are satisfied.

An eleventh invention of the present invention is the EL displayapparatus according to the seventh invention of the present invention,characterized in that if the number of gradations is K, if channellength of the unit transistor of the unit transistor is L (μm), and ifchannel width is W (μm), a condition ({square root}{square root over ()}(K/16))≦L/W≦({square root}{square root over ( )}(K/16))×20 issatisfied.

A twelfth invention of the present invention is an EL display apparatuscomprising:

-   -   a first EL display panel which has a first display screen;    -   a second EL display panel which has a second display screen; and    -   a flexible board which connects source signal lines of the first        EL display panel with source signal lines of the second EL        display panel,    -   characterized in that if channel width of driver transistors        which drive pixels is W (μm) and channel length is L (μm), W/L        differs between the driver transistor which drives pixels in the        first display screen and the driver transistor which drives        pixels in the second display screen.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a pixel in a display panel according to thepresent invention;

FIG. 2 is a block diagram of a pixel in a display panel according to thepresent invention;

FIG. 3 is an explanatory diagram illustrating operation of a displaypanel according to the present invention;

FIG. 4 is an explanatory diagram illustrating operation of a displaypanel according to the present invention;

FIG. 5 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 6 is a block diagram of a display apparatus according to thepresent invention;

FIG. 7 is an explanatory diagram illustrating a manufacturing method ofa display panel according to the present invention;

FIG. 8 is a block diagram of a display apparatus according to thepresent invention;

FIG. 9 is a block diagram of a display apparatus according to thepresent invention;

FIG. 10 is a sectional view of a display panel according to the presentinvention;

FIG. 11 is a sectional view of a display panel according to the presentinvention;

FIG. 12 is an explanatory diagram illustrating a display panel accordingto the present invention;

FIG. 13 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 14 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 15 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 16 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 17 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 18 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 19 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 20 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 21 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 22 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 23 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 24 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 25 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 26 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 27 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 28 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 29 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 30 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 31 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 32 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 33 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 34 is a block diagram of a display apparatus according to thepresent invention;

FIG. 35 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 36 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 37 is a block diagram of a display apparatus according to thepresent invention;

FIG. 38 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 39 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 40 is a block diagram of a display apparatus according to thepresent invention;

FIG. 41 is a block diagram of a display apparatus according to thepresent invention;

FIG. 42 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 43 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 44 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 45 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 46 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 47 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 48 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 47 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 48 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 47 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 48 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 47 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 48 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 49 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 50 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 51 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 52 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 53 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 54 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 55 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 56 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 57 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 58 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 59 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 60 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 61 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 62 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 63 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 64 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 65 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 66 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 67 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 68 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 69 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 70 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 71 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 72 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 73 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 74 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 75 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 76 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 77 is an explanatory diagram illustrating a drive circuit accordingto the present invention;

FIG. 78 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 79 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 80 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 81 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 82 is an explanatory diagram illustrating a drive method of adisplay apparatus according to the present invention;

FIG. 83 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 84 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 85 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 86 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 87 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 88 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 89 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 90 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 91 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 92 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 93 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 94 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 95 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 96 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 97 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 98 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 99 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 100 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 101 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 102 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 103 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 104 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 105 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 106 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 107 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 108 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 109 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 110 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 111 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 112 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 113 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 114 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 115 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 116 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 117 is a block diagram of a pixel in a display panel according tothe present invention;

FIG. 118 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 119 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 120 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 121 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 122 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 123 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 124 is an explanatory diagram illustrating a drive circuit of adisplay apparatus according to the present invention;

FIG. 125 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 126 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 127 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 128 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 129 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 130 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 131 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 132 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 133 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 134 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 135 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 136 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 137 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 138 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 139 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 140 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 141 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 142 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 143 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 144 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 145 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 146 is an explanatory diagram illustrating a drive method of adisplay panel according to the present invention;

FIG. 147 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 148 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 149 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 150 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 151 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 152 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 153 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 154 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 155 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 156 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 157 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 158 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 159 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 160 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 161 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 162 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 163 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 164 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 165 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 166 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 167 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 168 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 169 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 170 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 171 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 172 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 173 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 174 is an explanatory diagram illustrating a display apparatusaccording to the present invention;

FIG. 175 is an explanatory diagram illustrating a source driver ICaccording to the present invention;

FIG. 176 is an explanatory diagram illustrating a source driver ICaccording to the present invention.

DESCRIPTION OF SYMBOLS

-   11 Transistor (thin-film transistor)-   12 Gate driver IC (circuit)-   14 Source driver IC (circuit)-   15 EL (element) (light-emitting element)-   16 Pixel-   17 Gate signal line-   18 Source signal line-   19 Storage capacitance (additional capacitor, additional    capacitance)-   50 Display screen-   51 Write pixel (row)-   52 Non-display pixel (non-display area, non-illuminated area)-   53 Display pixel (display area, illuminated area)-   61 Shift register-   62 Inverter-   63 Output buffer-   71 Array board (display panel)-   72 Laser irradiation range (laser spot)-   73 Positioning marker-   74 Glass substrate (array board)-   81 Control IC (circuit)-   82 Power supply IC (circuit)-   83 Printed board-   84 Flexible board-   85 Sealing lid-   86 Cathode wiring-   87 Anode wiring (Vdd)-   88 Data signal line-   89 Gate control signal line-   101 Bank (rib)-   102 Interlayer insulating film-   104 Contact connector-   105 Pixel electrode-   106 Cathode electrode-   107 Desiccant-   108 λ/4 plate-   109 Polarizing plate-   111 Thin encapsulation film-   271 Dummy pixel (row)-   341 Output stage circuit-   371 OR circuit-   401 Illumination control line-   471 Reverse bias line-   472 Gate potential control line-   451 Electronic regulator circuit-   452 SD (source-drain) short circuit of a transistor-   471, 472, 473 Current source (transistor)-   481 Switch (on/off means)-   484 Current source (unit transistor)-   483 Internal wiring-   491 Electronic regulator-   521 Transistor group-   531 Resister-   532 Decoder circuit-   533 Level shifter circuit-   541 Padder circuit-   551 D/A converter-   552 Operational amplifier-   562 Inverter-   581 Gate wiring-   631 Sleep switch (reference current on/off means)-   651 Counter-   652 NOR-   653 AND-   654 Current output circuit-   655 Switch-   671 Coincidence circuit-   681 Input/output pad-   691 Reference current circuit-   692 Current control circuit-   701 Temperature detection means-   702 Temperature control circuit-   711 Unit gate output circuit-   1121 Coil (transformer)-   1122 Control circuit-   1123 Diode-   1124 Capacitor-   1125 Resister-   1126 Transistor-   1131 Switching circuit (analog switch)-   1251 Output switching circuit-   1252 Changeover switch-   1501 Analog switch-   1502 Switch control line-   1503 Connection wiring-   1504 Cushioning sheet (plate)-   1521 Inverter-   1522 Connection terminal-   1571 Antenna-   1572 Key-   1573 Housing-   1574 Display panel-   1581 Eye ring-   1582 Magnifying lens-   1583 Convex lens-   1591 Supporting point (pivot point)-   1592 Taking lens-   1593 Storage section-   1594 Switch-   1601 Body-   1602 Photographic section-   1603 Shutter switch-   1611 Mounting frame-   1612 Leg-   1613 Mount-   1614 Fixed part-   1731 Control electrode-   1732 Video signal circuit-   1733 Electron emission protuberance-   1734 Holding circuit-   1735 On/off control circuit-   1741 Selection signal line-   1742 On/off signal line

MODE FOR CARRYING OUT THE INVENTION

Some parts of drawings herein are omitted and/or enlarged/reduced hereinfor ease of understanding and/or illustration. For example, in asectional view of a display panel shown in FIG. 11, a thin encapsulationfilm 111 and the like are shown as being fairly thick. On the otherhand, in FIG. 10, a sealing lid 85 is shown as being thin. Some partsare omitted. For example, although the display panel according to thepresent invention requires a phase film such as a circular polarizingplate to prevent reflection, the phase film is omitted in drawingsherein. This also applies to the drawings below. Besides, the same orsimilar forms, materials, functions, or operations are denoted by thesame reference numbers or characters.

Incidentally, what is described with reference to drawings or the likecan be combined with other examples or the like even if not notedspecifically. For example, a touch panel or the like can be attached toa display panel in FIG. 8 to provide an information display apparatusshown in FIGS. 157 and 159 to 161. Also, a magnifying lens 1582 can bemounted to configure a view finder (see FIG. 58) used for a video camera(see FIG. 159, etc.) or the like. Also, drive methods described withreference to FIGS. 4, 15, 18, 21, 23, 29, 30, 35, 36, 40, 41, 44, 100,etc. can be applied to any display apparatus or display panel accordingto the present invention.

Also, thin-film transistors are cited herein as driver transistors 11and switching transistors 11, this is not restrictive. Thin-film diodes(TFDs) or ring diodes may be used instead. Also, the present inventionis not limited to thin-film elements, and transistors formed on siliconwafers may also be used. In that case, an array board 71 can be made ofa silicon wafer. Needless to say, FETs, MOS-FETs, MOS transistors, orbipolar transistors may also be used. They are basically, thin-filmtransistors. It goes without saying that the present invention may alsouse varistors, thyristors, ring diodes, photodiodes, phototransistors,or PLZT elements. That is, the transistor element 11, gate drivercircuit 12, and source driver circuit 14 according to the presentinvention can use any of the above elements.

An EL panel according to the present invention will be described belowwith reference to drawings. As shown in FIG. 10, an organic EL displaypanel consists of a glass substrate (array board) 71, transparentelectrodes 105 formed as pixel electrodes, at least one organicfunctional layer (EL layer) 15, and a metal electrode (reflective film)(cathode) 106, which are stacked one on top of another, where theorganic functional layer consists of an electron transport layer,light-emitting layer, positive hole transport layer, etc. The organicfunctional layer (EL layer) 15 emits light when a positive voltage isapplied to the anode or transparent electrodes (pixel electrodes) 105and a negative voltage is applied to the cathode or metal electrode(reflective electrode) 106, i.e. when a direct current is appliedbetween the transparent electrodes 105 and metal electrode 106.

Preferably, the metal electrode 106 is made of metal with a small workfunction, such as lithium, silver, aluminum, magnesium, indium, copper,or an alloy thereof. In particular, it is preferable to use, forexample, an Al—Li alloy. The transparent electrodes 105 may be made of,conductive materials with a large work function such as ITO, or gold andthe like. If gold is used as an electrodematerial, the electrodes becometranslucent. Incidentally, IZO or other material may be used instead ofITO. This also applies to other pixel electrodes 105.

Incidentally, a desiccant 107 is placed in a space between the sealinglid 85 and array board 71. This is because the organic EL film 15 isvulnerable to moisture. The desiccant 107 absorbs water penetrating asealant and thereby prevents deterioration of the organic EL film 15.

Although the glass lid 85 is used for sealing in FIG. 10, the film 111(this may be a thin film, i.e., a thin encapsulation film) may be usedfor sealing as shown in FIG. 11. The encapsulation film (thinencapsulation film) 111 may be, for example, an electrolytic capacitorfilm on which DLC (diamond-like carbon) is vapor-deposited. This filmfeatures extremely low moisture penetration (high moisture resistance)It is used as the thin encapsulation film 111. Also, it goes withoutsaying that DLC (diamond-like carbon) film may be vapor-depositeddirectly on a surface of the metal electrode 106. Besides, the thinencapsulation film may be formed by laminating thin resin films andmetal films.

Desirably, film thickness of the thin film is such that n·d is equal toor less than main emission wavelength λ of the EL element 15 (where n isthe refraction factor of the thin film, or the sum of refraction factorsif two or more thin films are laminated (n·d of each thin film iscalculated) d is the film thickness of the thin film, or the sum ofrefraction factors if two or more thin films are laminated). Bysatisfying this condition, it is possible to more than double theefficiency of light extraction from the EL element 15 compared to when aglass substrate is used for sealing. Also, an alloy, mixture, orlaminate of aluminum and silver may be used.

A technique which uses a thin encapsulation film 111 for sealing insteadof a sealing lid 85 as described above is called thin filmencapsulation. In the case of “underside extraction (see FIG. 10; lightis extracted in the direction of the arrow in FIG. 10)” in which lightis extracted from the side of the array board 71, thin filmencapsulation involves forming an EL film and then forming an aluminumelectrode which will serve as a cathode on the EL film. Then, a resinlayer is formed as a cushioning layer on the aluminum layer. Anorganicmaterial such as acrylic or epoxy may be used for a cushioning layer.Suitable film thickness is from 1 μm to 10 μm (both inclusive). Morepreferably, the film thickness is from 2 μm to 6 μm (both inclusive).The encapsulation film 74 is formed on the cushioning film. Without thecushioning film, structure of the EL film would be deformed by stress,resulting in streaky defects. As described above, the thin encapsulationfilm 111 may be made, for example, of DLC (diamond-like carbon) or anelectrolytic capacitor of a laminar structure (structure consisting ofthin dielectric films and aluminum films vapor-deposited alternately).

In the case of “topside extraction (see FIG. 11; light is extracted inthe direction of the arrow in FIG. 11)” in which light is extracted fromthe side of the EL layer 15, thin film encapsulation involves formingthe EL film 15 and then forming an Ag—Mg film 20 angstrom (inclusive) to300 angstrom thick on the EL film 15 to serve as a cathode (anode) Atransparent electrode such as ITO is formed on the film to reduceresistance. Then, a resin layer is formed as a cushioning layer on theelectrode film. A thin encapsulation film 111 is formed on thecushioning film.

Half the light produced by the organic EL layer 15 is reflected by themetal electrode 106 and emitted through the array board 71. However, themetal electrode 106 reflects extraneous light, resulting in glare, whichlowers display contrast. To deal with this situation, a λ/4 phase plate108 and polarizing plate (polarizing film) 109 are placed on the arrayboard 71. These are generally called circular polarizing plates(circular polarizing sheets).

Incidentally, if the pixels are reflective electrodes, the lightproduced by the organic EL layer 15 is emitted upward. Thus, needless tosay, the phase plate 108 and polarizing plate 109 are placed on the sidefrom which light is emitted. Reflective pixels can be obtained by makingpixel electrodes 105 from aluminum, chromium, silver, or the like. Also,by providing projections (or projections and depressions) on a surfaceof the pixel electrodes 105, it is possible to increase an interfacewith the organic EL layer 15, and thereby increase the light-emittingarea, resulting in improved light-emission efficiency. Incidentally, thereflective film which serves as the cathode 106 (anode 105) is made as atransparent electrode. If reflectance can be reduced to 30% or less, nocircular polarizing plate is required. This is because glare is reducedgreatly. Light interference is reduced as well.

Preferably, LDD (low doped drain) structure is used for the transistors11. The EL elements will be described herein taking organic EL elements(known by various abbreviations including OEL, PEL, PLED, OLED) 15 as anexample, but this is not restrictive and inorganic EL elements may beused as well.

An organic EL display panel of active-matrix type must satisfy twoconditions: that it is capable of selecting a specific pixel and givenecessary display information and that it is capable of passing currentthrough the EL element throughout one frame period.

To satisfy the two conditions, in a conventional organic EL pixelconfiguration shown in FIG. 46, a switching transistor is used as afirst transistor 11 b to select the pixel and a driver transistor isused as a second transistor 11 a to supply current to an EL element (ELfilm) 15.

To display a gradation using this configuration, a voltage correspondingto the gradation must be applied the gate of the driver transistor 11 a.Consequently, variations in a turn-on current of the driver transistor11 a appear directly in display.

The turn-on current of a transistor is extremely uniform if thetransistor is monocrystalline. However, in the case of a low-temperaturepolycrystalline transistor formed on an inexpensive glass substrate bylow-temperature polysilicon technology at a temperature not higher than450, its threshold varies in a range of ±0.2 V to 0.5 V. The turn-oncurrent flowing through the driver transistor 11 a varies accordingly,causing display irregularities. The irregularities are caused not onlyby variations in the threshold voltage, but also by mobility of thetransistor and thickness of a gate insulating film. Characteristics alsochange due to degradation of the transistor 11.

This phenomenon is not limited to low-temperature polysilicontechnologies, and can occur in transistors formed on semiconductor filmsgrown in solid-phase (CGS) by high-temperature polysilicon technology ata process temperature of 450 degrees (centigrade) or higher. Besides,the phenomenon can occur in organic transistors and amorphous silicontransistors.

As described below, the present invention provides a configuration orscheme which can accommodate the above technologies. Description will begiven herein mainly of transistors produced by the low-temperaturepolysilicon technology.

In a method which displays gradations by the application of voltage asshown in FIG. 46, device characteristics must be controlled strictly toobtain a uniform display. However, current low-temperaturepolycrystalline polysilicon transistors or the like cannot satisfy aspecification which prescribes that variations be kept within apredetermined range.

Each pixel structure in an EL display panel according to the presentinvention comprises at least four transistors 11 and an EL element asshown concretely in FIG. 1. Pixel electrodes are configured to overlapwith a source signal line. Specifically, the pixel electrodes 105 areformed on an insulating film or planarized acrylic film formed on thesource signal line 18 for insulation. A structure in which pixelelectrodes overlap with at least part of the source signal line 18 isknown as a high aperture (HA) structure. This reduces unnecessary lightinterference and allows proper light emission.

When the gate signal line (first scanning line) 17 a is activated (aturn-on voltage is applied), a current to be passed through the ELelement 15 is delivered from the source driver circuit 14 via the drivertransistor 11 a and switching transistor 11 c of the EL element 15.Also, upon activation of (application of a turn-on voltage to) the gatesignal line 17 a, the transistor 11 b opens to cause a short circuitbetween gate and drain of the transistor 11 a and gate voltage (or drainvoltage) of the transistor 11 a is stored in a capacitor (storagecapacitance, additional capacitance) 19 connected between the gate anddrain of the transistor 11 a (see FIG. 3(a)).

Preferably, the capacitor (storage capacitance) 19 should be from 0.2 pFto 2 pF both inclusive. More preferably, the capacitor (storagecapacitance) 19 should be from 0.4 pF to 1.2 pF both inclusive. Thecapacity of the capacitor 19 is determined taking pixel size intoconsideration. If the capacity needed for a single pixel is Cs (pF) andan area (rather than an aperture ratio) occupied by the pixel is Sp(square μm), a condition 500/S≦Cs≦20000/S, and more preferably acondition 1000/Sp≦Cs≦10000/Sp should be satisfied. Since gate capacityof the transistor is small, Q as referred to here is the capacity of thestorage capacitance (capacitor) 19 alone.

The gate signal line 17 a is deactivated (a turn-off voltage isapplied), a gate signal line 17 b is activated, and a current path isswitched to a path which includes the first transistor 11 a, atransistor 11 d connected to the EL element 15, and the EL element 15 todeliver the stored current to the EL element 15 (see FIG. 3(b)).

In this circuit, a single pixel contains four transistors 11. The gateof the transistor 11 a is connected to the source of the transistor 11b. The gates of the transistors 11 b and 11 c are connected to the gatesignal line 17 a. The drain of the transistor 11 b is connected to thesource of the transistor 11 c and source of the transistor 11 d. Thedrain of the transistor 11 c is connected to the source signal line 18.The gate of the transistor 11 d is connected to the gate signal line 17b and the drain of the transistor 11 d is connected to the anodeelectrode of the EL element 15.

Incidentally, all the transistors in FIG. 1 are P-channel transistors.Compared to N-channel transistors, P-channel transistors have more orless lower mobility, but they are preferable because they are moreresistant to voltage and degradation. However, the EL element accordingto the present invention is not limited to P-channel transistors and thepresent invention may employ N-channel transistors alone. Also, thepresent invention may employ both N-channel and P-channel transistors.

Optimally, P-channel transistors should be used for all the transistors11 composing pixels as well as for the built-in gate driver circuits 12.By composing an array solely of P-channel transistors, it is possible toreduce the number of masks to 5, resulting in low costs and high yields.

To facilitate understanding of the present invention, the configurationof the EL element according to the present invention will be describedbelow with reference to FIG. 3. The EL element according to the presentinvention is controlled using two timings. The first timing is the onewhen required current values are stored. Turning on the transistor 11 band transistor 11 c with this timing provides an equivalent circuitshown in FIG. 3(a). A predetermined current Iw is applied from signallines. This makes the gate and drain of the transistor 11 a connected,allowing the current Iw to flow through the transistor 11 a andtransistor 11 c. Thus, the gate-source voltage of the transistor 11 a issuch that allows 11 to flow.

The second timing is the one when the transistor 11 a and transistor 11c are closed and the transistor 11 d is opened. The equivalent circuitavailable at this time is shown in FIG. 3(b). The source-gate voltage ofthe transistor 11 a is maintained. In this case, since the transistor 11a always operates in a saturation region, the current Iw remainsconstant.

Results of this operation are shown in FIG. 5. Specifically, referencenumeral 51 a in FIG. 5(a) denotes a pixel (row) (write pixel row)programmed with current at a certain time point in a display screen 50.The pixel row 51 a is non-illuminated (non-display pixel (row)) asillustrated in FIG. 5(b). Other pixels (rows) are display pixels (rows)53 (current flows through the EL elements 15 of the pixels 16 in thedisplay area 53, causing the EL elements 15 to emit light).

In the pixel configuration in FIG. 1, the programming current Iw flowsthrough the source signal line 18 during current programming as shown inFIG. 3(a). The current Iw flows through the transistor 11 a and voltageis set (programmed) in the capacitor 19 in such a way as to maintain thecurrent Iw. At this time, the transistor 11 d is open (off).

During a period when the current flows through the EL element 15, thetransistors 11 c and 11 b turn off and the transistor 11 d turns on asshown in FIG. 3(b). Specifically, a turn-off voltage (Vgh) is applied tothe gate signal line 17 a, turning off the transistors 11 b and 11 c. Onthe other hand, a turn-on voltage (Vgl) is applied to the gate signalline 17 b, turning on the transistor 11 d.

A timing chart is shown in FIG. 4. The subscripts in brackets in FIG. 4(e.g., (1)) indicate pixel row numbers. Specifically, a gate signal line17 a (1) denotes a gate signal line 17 a in a pixel row (1). Also, *H(where “*” is an arbitrary symbol or numeral and indicates a horizontalscanning line number) in the top row in FIG. 4 indicates a horizontalscanning period. Specifically, 1 H is a first horizontal scanningperiod. Incidentally, the items (1 H number, 1-H cycle, order of pixelrow numbers, etc.) described above are intended to facilitateexplanation and are not intended to be restrictive.

As can be seen from FIG. 4, in each selected pixel row (it is assumedthat the selection period is 1 H), when a turn-on voltage is applied tothe gate signal line 17 a, a turn-off voltage is applied to the gatesignal line 17 b. During this period, no current flows through the ELelement 15 (non-illuminated). In non-selected pixel rows, a turn-offvoltage is applied to the gate signal line 17 a and a turn-on voltage isapplied to the gate signal line 17 b. During this period, a currentflows through the EL element 15 (illuminated).

Incidentally, the gate of the transistor 11 a and gate of the transistor11 c are connected to the same gate-signal line 11 a. However, the gateof the transistor 11 a and gate of the transistor 11 c may be connectedto different gate signal lines 11 (see FIG. 32). Then, one pixel willhave three gate signal lines (two in the configuration in FIG. 1). Bycontrolling ON/OFF timing of the gate of the transistor 11 b and ON/OFFtiming of the gate of the transistor 11 c separately, it is possible tofurther reduce variations in the current value of the EL element 15 dueto variations in the transistor 11 a.

By sharing the gate signal line 17 a and gate signal line 17 b and usingdifferent conductivity types (N-channel and P-channel) for thetransistors 11 c and 11 d, it is possible to simplify the drive circuitand improve the aperture ratio of pixels.

With this configuration, a write paths from signal lines are turned offaccording to operation timing of the present invention That is, when apredetermined current is stored, an accurate current value is not storedin a capacitance (capacitor) between the source (S) and gate (G) of thetransistor 11 a if a current path is branched. By using differentconductivity types for the transistors 11 c and 11 d and controllingtheir thresholds, it is possible to ensure that when scanning lines areswitched, the transistor 11 d is turned on after the transistor 11 c isturned off.

In that case, however, since the thresholds of the transistors must becontrolled accurately, it is necessary to pay attention to processes.The circuit described above can be implemented using four transistors atthe minimum, but even if more than four transistors including atransistor 11 e are cascaded for more accurate timing control or forreduction of mirror effect (described later), the principle of operationis the same. By adding the transistor 11 e, it is possible to deliverprogramming current to the EL element 15 more precisely via thetransistor 11 c.

Incidentally, the pixel configuration according to the present inventionis not limited to those shown in FIGS. 1 and 2. For example, pixels maybe configured as shown in FIG. 113. FIG. 113 lacks the transistor 11 dunlike the configuration in FIG. 1. Instead, a changeover switch 1131 isformed or placed. The switch 11 d in FIG. 1 functions to turn on and off(pass and shut off) the current delivered from the driver transistor 11a to the EL element 15. As also described in subsequent examples, theon/off control function of the transistor 11 d constitutes an importantpart of the present invention. The configuration in FIG. 113 achievesthe on/off function without using the transistor 11 d.

In FIG. 113, a terminal a of the changeover switch 1131 is connected toanode voltage Vdd. Incidentally, the voltage applied to the terminal ais not limited to the anode voltage Vdd. It may be any voltage that canturn off the current flowing through the EL element 15.

A terminal b of the changeover switch 1131 is connected to cathodevoltage (indicated as ground in FIG. 113). Incidentally, the voltageapplied to the terminal b is not limited to the cathode voltage. It maybe any voltage that can turn on the current flowing through the ELelement 15.

A terminal c of the changeover switch 1131 is connected with a cathodeterminal of the EL element 15. Incidentally, the changeover switch 1131may be of any type as long as it has a capability to turn on and off thecurrent flowing through the EL element 15. Thus, its installationlocation is not limited to the one shown in FIG. 113 and the switch maybe located anywhere on the path through which current is delivered tothe EL element 15. Also, the switch is not limited by its functionalityas long as the switch can turn on and off the current flowing throughthe EL element 15. In short, the present invention can have any pixelconfiguration as long as switching means capable of turning on and offthe current flowing through the EL element 15 is installed on thecurrent path for the EL element 15.

Also, the term “off” here does not mean a state in which no currentflows, but it means a state in which the current flowing through the ELelement 15 is reduced to below normal. The items mentioned above alsoapply to other configurations of the present invention.

The changeover switch 1131 will require no explanation because it can beimplemented easily by a combination of P-channel and N-channeltransistors. For example, it can be implemented by two circuits ofanalog switches. Of course, the switch 1131 can be constructed of onlyP-channel or N-channel transistors because it only turns off the currentflowing through the EL element 15.

When the switch 1131 is connected to the terminal a, the Vdd voltage isapplied to the cathode terminal of the EL element 15. Thus, current doesnot flow through the EL element 15 regardless of the voltage state ofvoltage held by the gate terminal G of the driver transistor 11 a.Consequently, the EL element 15 is non-illuminated.

When the switch 1131 is connected to the terminal b, the GND voltage isapplied to the cathode terminal of the EL element 15. Thus, currentflows through the EL element 15 according to the state of voltage heldby the gate terminal G of the driver transistor 11 a. Consequently, theEL element 15 is illuminated.

Thus, in the pixel configuration shown in FIG. 113, no switchingtransistor 11 d is formed between the driver transistor 11 a and the ELelement 15. However, it is possible to control the illumination of theEL element 15 by controlling the switch 1131.

In the pixel configurations shown in FIGS. 1, 2, etc., one pixelcontains one driver transistor 11 a. However, the present invention isnot limited to this and one pixel may contain two or more drivertransistors 11 a. An example is shown in FIG. 116, where one pixelcontains two driver transistors 11 a 1 and 11 a 2, whose gate terminalsare connected to a common capacitor 19. By using a plurality of drivertransistors 11 a, it is possible to reduce variations in programmingcurrent. The other part of the configuration is the same as those shownin FIG. 1 and the like, and thus description thereof will be omitted.

In FIGS. 1 and 2, the current outputted by the driver transistor 11 a ispassed through the EL element 15 and turned on and off by the switchingtransistor 11 d formed between the driver transistor 11 a and the ELelement 15. However, the present invention is not limited to this. Forexample, another configuration is illustrated in FIG. 117.

In the example shown in FIG. 117, the current delivered to the ELelement 15 is controlled by the driver transistor 11 a. The currentflowing through the EL element 15 is turned on and off by the switchingelement 11 d placed between the Vdd terminal and EL element 15. Thus,according to the present invention, the switching element 11 d may beplaced anywhere as long as it can control the current flowing throughthe EL element 15.

Variations in the characteristics of the transistor 11 a are correlatedto the transistor size. To reduce the variations in the characteristics,preferably the channel length of the first transistor 11 a is from 5 μmto 100 μm (both inclusive). More preferably, it is from 10 μm to 50 μm(both inclusive). This is probably because a long channel length Lincreases grain boundaries contained in the channel, reducing electricfields, and thereby suppressing kink effect.

Thus, according to the present invention, circuit means which controlsthe current flowing through the EL element 15 is constructed, formed, orplaced on the path along which current flows into the EL element 15 andthe path along which current flows out of the EL element 15 (i.e., thecurrent path for the EL element 15).

Even in the case of current mirroring, a type of current programming, byforming or placing a transistor 11 g as a switching element between thedriver transistor 11 b and EL element 15 as shown in FIG. 114, it ispossible to turn on and off (control) the current flowing through the ELelement 15. Of course, the transistor 11 g may be substituted with theswitch 1131 in FIG. 113.

Incidentally, although the switching transistors 11 d and 11 c in FIG.114 are connected to a single gate signal line 17 a, the switchingtransistor 11 c may be controlled by a gate signal line 17 a 1 and theswitching transistor 11 d may be controlled by a gate signal line 17 a 2as shown in FIG. 115. The configuration in FIG. 115 makes pixel 16control more versatile.

As shown in FIG. 42(a), the transistors 11 b and 11 c may be N-channeltransistors. Also, as shown in FIG. 42(b), the transistors 11 c and 11 dmay be P-channel transistors.

An object of the present invention is to propose a circuit configurationin which variations in transistor characteristics do not affect display.Four or more transistors are required for that. When determining circuitconstants using transistor characteristics, it is difficult to determineappropriate circuit constants unless the characteristics of the fourtransistors are not consistent. Both thresholds of transistorcharacteristics and mobility of the transistors vary depending onwhether the channel direction is horizontal or vertical with respect tothe longitudinal axis of laser irradiation. Incidentally, variations aremore of the same in both cases. However, the mobility and averagethreshold vary between the horizontal direction and vertical direction.Thus, it is desirable that all the transistors in a pixel have the samechannel direction.

Also, if the capacitance value of the storage capacitance 19 is Cs andthe turn-off current value of the second transistor 11 b is Ioff,preferably the following equation is satisfied.3<Cs/Ioff<24

More preferably the following equation is satisfied.6<Cs/Ioff<18

By setting the turn-off current of the transistor 11 b to 5 pA or less,it is possible to reduce changes in the current flowing through the ELto 2% or less. This is because when leakage current increases, electriccharges stored between the gate and source (across the capacitor) cannotbe held for one field with no voltage applied. Thus, the larger thestorage capacity of the capacitor 19, the larger the permissible amountof the turn-off current. By satisfying the above equation, it ispossible to reduce fluctuations in current values between adjacentpixels to 2% or less.

Also, preferably transistors composing an active matrix are p-channelpolysilicon thin-film transistors and the transistor 11 b is a dual-gateor multi-gate transistor. As high an ON/OFF ratio as possible isrequired of the transistor 11 b, which acts as a source-drain switch forthe transistor 11 a. By using a dual-gate or multi-gate structure forthe transistor 11 b, it is possible to achieve a high ON/OFF ratio.

The semiconductor films composing the transistors 11 in the pixel 16 aregenerally formed by laser annealing in low-temperature polysilicontechnology. Variations in laser annealing conditions result invariations in transistor 11 characteristics. However, if thecharacteristics of the transistors 11 in the pixel 16 are consistent, itis possible to drive the pixel using current programming such as the oneshown in FIG. 1 so that a predetermined current will flow through the ELelement 15. This is an advantage lacked by voltage programming.Preferably the laser used is an excimer laser.

Incidentally, the semiconductor film formation according to the presentinvention is not limited to the laser annealing method. The presentinvention may also use a heat annealing method and a method whichinvolves solid-phase (CGS) growth. Besides, the present invention is notlimited to the low-temperature polysilicon technology and may usehigh-temperature polysilicon technology. Also, the semiconductor filmsmay be formed by amorphous silicon technology.

To deal with this problem, the present invention moves a laser spot(laser irradiation range) 72 in parallel to the source signal line 18 asshown in FIG. 7. Also, the laser spot 72 is moved in such a way as toalign with one pixel row. Of course, the number of pixel rows is notlimited to one. For example, laser may be shot by treating RGB in FIG.55 (three pixel columns in this case) as a single pixel 16. Also, lasermay be directed at two or more pixels at a time. Needless to say, movinglaser irradiation ranges may overlap (it is usual for moving laserirradiation ranges to overlap).

Pixels are constructed in such a way that three pixels of RGB will forma square shape. Thus, each of the R, G, B pixels has oblong shape.Consequently, by performing annealing using an oblong laser spot 72, itis possible to eliminate variations in the characteristics of thetransistors 11 within each pixel. Also, the characteristics (mobility,Vt, S value, etc.) of the transistors 11 connected to the same sourcesignal line 18 can be made uniform (i.e., although the transistors 11connected to adjacent source signal lines 18 may differ incharacteristics, the characteristics of the transistors 11 connected tothe same source signal line can be made almost equal).

In the configuration shown in FIG. 7, three panels are placed lengthwisewithin the length of the laser spot 72. An annealing apparatus whichemits the laser spot 72 recognizes positioning markers 73 a and 73 b ona glass substrate 74 (automatic positioning based on patternrecognition) and moves the laser spot 72. The positioning markers 73 arerecognized by a pattern recognition apparatus. The annealing apparatus(not shown) recognizes the positioning markers 73 and determines thelocation of the pixel column (makes the laser irradiation range 72parallel to the source signal line 18). It emits the laser spot 72 insuch a way as to overlap with the location of each pixel column forsequential annealing.

Preferably, the laser annealing method (which involves emitting a linearlaser spot in parallel to the source signal line 18) described withreference to FIG. 7 is used for current programming of an organic ELdisplay panel, in particular. This is because the transistors 11 placedin the direction parallel to the source signal line have the samecharacteristics (the characteristics of the pixel transistors adjacentin the longitudinal direction are quite similar to each other). Thisreduces changes in the voltage level of the source signal lines when thepixels are driven by current, and thus reduces the chances ofinsufficient write current.

For example, in the case of white raster display, since almost the samecurrent is passed through the transistors 11 a in adjacent pixels, thecurrent outputted from the source driver IC 14 does not have significantamplitude changes. If the transistors 11 a in FIG. 1 have the samecharacteristics and the currents used for current programming of pixelshave the same value within the pixel column, the potential of the sourcesignal line 18 during the current programming is constant. Thus, nopotential fluctuation occurs in the source signal line 18. If thetransistors 11 a connected to the same source signal line 18 have almostthe same characteristics, there should be no significant potentialfluctuation in the source signal line 18. This is also true to othercurrent-programmable pixel configurations such as the one shown in FIG.38 (thus, it is preferable to use the manufacturing method shown in FIG.7).

A method which involves programming two or more pixel rowssimultaneously and which are described with reference to FIG. 27, 30,etc. can achieve a uniform image display (because the method is notprone to display irregularities due mainly to variations in transistorcharacteristics). In the case of FIG. 27, etc., since a plurality ofpixel rows are selected simultaneously, if the transistors in adjacentpixel rows are uniform, irregularities in the characteristics of thetransistors placed in the lengthwise direction can be absorbed by thesource driver circuit 14.

Incidentally, although an IC chip is illustrated in FIG. 7 as beingstacked on the source driver circuit 14, this is not restrictive and itgoes without saying that the source driver circuit 14 may be formed inthe same process as the pixel 16.

The present invention, in particular, ensures that a voltage thresholdVth2 of the driver transistor 11 b will not fall below a voltagethreshold Vth1 of the corresponding driver transistor 11 a in the pixel.For example, gate length L2 of the transistor 11 b is made longer thangate length L1 of the transistor 11 a so that Vth2 will not fall belowVth1 even if process parameters of these thin-film transistors change.This makes it possible to suppress subtle current leakage.

Incidentally, the items mentioned above also apply to pixelconfiguration of a current mirror shown in FIG. 38. The pixel in FIG. 38consists of a driver transistor 11 a through which a signal currentflows, a driver transistor 11 b which controls drive current flowingthrough a light-emitting element such as an EL element 15, a transistor11 c which connects or disconnects a pixel circuit and data line “data”by controlling a gate signal line 17 a 1, a switching transistor 11 dwhich shorts the gate and drain of the transistor 11 a during a writeperiod by controlling a gate signal line 17 a 2, a capacitance C19 whichholds gate-source voltage of the transistor 11 a after application ofvoltage, the EL element 15 serving as a light-emitting element, etc.

In FIG. 38, the transistors 11 c and 11 d are N-channel transistors andother transistors are P-channel transistors, but this is only exemplaryand are not restrictive. A capacitance Cs has its one end connected tothe gate of the transistor 11 a, and the other end to Vdd (power supplypotential), but it may be connected to any fixed potential instead ofVdd. The cathode (negative pole) of the EL element 15 is connected tothe ground potential.

Next, the EL display panel or EL display apparatus of the presentinvention will be described. FIG. 6 is an explanatory diagram whichmainly illustrates a circuit of the EL display apparatus. Pixels 16 arearranged or formed in a matrix. Each pixel 16 is connected with a sourcedriver circuit 14 which outputs current for use in current programmingof the pixel. In an output stage of the source driver circuit 14 arecurrent mirror circuits (described later) corresponding to the bit countof a video signal. For example, if 64 gradations are used, 63 currentmirror circuits are formed on respective source signal lines so as toapply desired current to the source signal lines 18 when an appropriatenumber of current mirror circuits is selected (see FIG. 48).

Incidentally, the minimum output current of one current mirror circuitis from 10 nA to 50 nA (both inclusive). Preferably, the minimum outputcurrent of the current mirror circuit should be from 15 nA to 35 nA(both inclusive) to secure accuracy of the transistors composing thecurrent mirror circuit in the source driver IC 14.

Besides, a precharge or discharge circuit is incorporated to charge ordischarge the source signal line 18 forcibly. Preferably, voltage(current) output values of the precharge or discharge circuit whichcharges or discharges the source signal line 18 forcibly can be setseparately for R, G, and B. This is because the thresholds of the ELelement 15 differ among R, G, and B (regarding the precharge circuitrefer to FIGS. 65 and 67 and its explanation).

Organic EL elements are known to have heavy temperature dependence(temperature characteristics). To adjust changes in emission brightnesscaused by the temperature characteristics, reference current is adjusted(varied) in an analog fashion by adding nonlinear elements such asthermistors or posistors to the current mirror circuits to vary outputcurrent and adjusting the changes due to the temperature characteristicswith the thermistors or the like.

According to the present invention, the source driver circuit 14 is madeof a semiconductor silicon chip and connected with a terminal on thesource signal line 18 of the array board 71 by glass-on-chip (COG)technology. The source driver circuit 14 can be mounted not only by theCOG technology. It is also possible to mount the source driver circuit14 by chip-on-film (COF) technology and connect it to the signal linesof the display panel. Regarding the driver IC, it may be made of threechips by constructing a power supply IC 82 separately.

On the other hand, the gate driver circuit 12 is formed bylow-temperature polysilicon technology. That is, it is formed in thesame process as the transistors in pixels. This is because the gatedriver circuit 12 has a simpler internal structure and lower operatingfrequency than the source driver circuit 14. Thus, it can be formedeasily even by low-temperature polysilicon technology and allows bezelwidth to be reduced. Of course, it is possible to construct the gatedriver circuit 12 from a silicon chip and mount it on the array board 71using the COG technology. Also, switching elements such as pixeltransistors as well as gate drivers may be formed by high-temperaturepolysilicon technology or may be formed of an organic material (organictransistors).

The gate driver circuit 12 incorporates a shift register circuit 61 afor a gate signal line 17 a and a shift register circuit 61 b for a gatesignal line 17 b. The shift register circuits 61 are controlled bypositive-phase and negative-phase clock signals (CLKxP and CLKxN) and astart pulse (STx) (see FIG. 6). Besides, it is preferable to add anenable (ENABL) signal which controls output and non-output from the gatesignal line and an up-down (UPDWN) signal which turns a shift directionupside down. Also, it is preferable to install an output terminal toensure that the start pulse is shifted by the shift register and isoutputted. Incidentally, shift timings of the shift registers arecontrolled by a control signal from a control IC 81. Also, the gatedriver circuit 12 incorporates a level shift circuit which level-shiftsexternal data.

Since the shift register circuits 61 have small buffer capacity, theycannot drive the gate signal lines 17 directly. Therefore, at least twoor more inverter circuits 62 are formed between each shift registercircuit 61 and an output gate 63 which drives the gate signal line 17.

The same applies to cases in which the source driver circuit 14 isformed on the array board 71 by polysilicon technology such aslow-temperature polysilicon technology. A plurality of inverter circuitsare formed between an analog switching gate such as a transfer gatewhich drives the source signal line 18 and the shift register of thesource driver circuit 14. The following matters (shift register outputand output stages which drive signal lines (inverter circuits placedbetween output stages such as output gates or transfer gates) are commonto the gate driver circuit and source driver circuit.

For example, although the output from the source driver circuit 14 isshown in FIG. 6 as being connected directly to the source signal line18, actually the output from the shift register of the source driver isconnected with multiple stages of inverter circuits, and the inverteroutputs are connected to analog switching gates such as transfer gates.

The inverter circuit 62 consists of a P-channel MOS transistor andN-channel MOS transistor. As described earlier, the shift registercircuit 61 of the gate driver circuit 12 has its output end connectedwith multiple stages of inverter circuits 62 and the final output isconnected to the output gate 63. Incidentally, the inverter circuit 62may be composed solely of P-channel MOS transistors. In that case,however, the circuit may be configured simply as a gate circuit ratherthan an inverter.

FIG. 8 is a block diagram of signal and voltage supplies on a displayapparatus according to the present invention or a block diagram of thedisplay apparatus. Signals (power supply wiring, data wiring, etc.) aresupplied from the control IC 81 to a source driver circuit 14 a via aflexible board 84.

In FIG. 8, a control signal for the gate driver circuit 12 is generatedby the control IC, level-shifted by the source driver circuit 14, andapplied to the gate driver circuit 12. Since drive voltage of the sourcedriver circuit 14 is 4 to 8 (V), the control signal with an amplitude of3.3 (V) outputted from the control IC 81 can be converted into a signalwith an amplitude of 5 (V) which can be received by the gate drivercircuit 12.

In FIG. 8 and the like, what is denoted by reference numeral 14 has beendescribed as a source driver, but instead of being a mere driver, it mayincorporate a power circuit, buffer circuit (including a circuit such asa shift register), data conversion circuit, latch circuit, commanddecoder, shifting circuit, address conversion circuit, image memory,etc. Needless to say, a three-side free configuration or otherconfiguration, drive system, etc. described with reference to FIG. 9 andthe like are also applicable to the configuration described withreference to FIG. 8 and the like.

When the display panel is used for information display apparatus such asa cell phone, it is preferable to mount (form) the source driver IC(circuit) 14 and gate driver IC (circuit) 12 on one side of the displaypanel as shown in FIG. 9 (incidentally, a configuration in which driverICs (circuits) are mounted (formed) on one side of a display panel isreferred to as a three-side free configuration (structure).Conventionally, the gate driver IC 12 is mounted on an X side of adisplay area and a source is mounted on a Y side). This makes it easy inthe design to center the center line of a display screen 50 on thedisplay apparatus and mount the driver ICs. Using the three-side freeconfiguration, the gate driver circuit may be produced byhigh-temperature polysilicon technology, low-temperature polysilicontechnology or the like (i.e., at least one of the source driver circuit14 and gate driver circuit 12 may be formed directly on the array board71 by polysilicon technology).

Incidentally, the three-side free configuration includes not only aconfiguration in which ICs are placed or formed directly on the arrayboard 71, but also a configuration in which a film (TCP, TAB, or othertechnology) with a source driver IC (circuit) 14 and gate driver IC(circuit) 12 mounted are pasted on one side (or almost one side) of thearray board 71. That is, the three-side free configuration includesconfigurations and arrangements in which two sides are left free of ICsand all similar configurations.

If the gate driver circuit 12 is placed beside the source driver circuit14 as shown in FIG. 9, the gate signal line 17 must be formed along theside C.

Incidentally, the thick solid line in FIG. 9, etc. indicates gate signallines 17 formed in parallel. Thus, as many gate signal lines 17 as thereare scanning signal lines are formed in parallel in part b (bottom ofthe screen) while a single gate signal line 17 is formed in part a (topof the screen).

Spacing between the gate signal lines 17 formed on the side C is from 5μm to 12 μm (both inclusive) If it is less than 5 μm, parasiticcapacitance will cause noise on adjacent gate signal lines. It has beenshown experimentally that parasitic capacitance has significant effectswhen the spacing is 7 μm or less. Furthermore, when the spacing is lessthan 5 μm, beating noise and other image noise appear intensely on thedisplay screen. In particular, noise generation differs between theright and left sides of the screen and it is difficult to reduce thebeating noise and other image noise. When the spacing exceeds 12 μm,bezel width D of the display panel becomes too large to be practical.

To reduce the image noise, a ground pattern (conductive pattern whichhas been fixed at a constant voltage or set generally at a stablepotential) can be placed under or above the gate signal lines 17.Alternatively, a separate shield plate (shield foil: a conductivepattern which has been fixed at a constant voltage or set generally at astable potential) may be placed on the gate signal lines 17.

The gate signal lines 17 on the side C in FIG. 9 may be formed of ITOelectrodes. However, to reduce resistance, preferably they are formed bylaminating ITO and thin metal films. Also preferably they are formed ofmetal films. When using an ITO laminate, a titanium film is formed onthe ITO, and a thin aluminum film or aluminum-molybdenum alloy film isformed on it. Alternatively, a chromium is formed on the ITO. For metalfilms, thin aluminum films or chromium films are used. This also appliesto other examples of the present invention.

Incidentally, although it has been stated with reference to FIG. 9 andthe like that the gate signal lines 17 are placed on one side of thedisplay area, this is not restrictive and they may be placed on bothsides. For example, the gate signal line 17 a may be placed (formed) onthe right side of the display screen 50 while the gate signal line 17 bmay be placed (formed) on the left side of the display screen 50. Thisalso applies to other examples.

Also, the source driver IC 14 and gate driver IC 12 may be integratedinto a single chip. Then, it suffices to mount only one IC chip on thedisplay panel. This also reduces implementation costs. Furthermore, thismakes it possible to simultaneously generate various voltages for use inthe single-chip driver IC.

Incidentally, although it has been stated that the source driver IC 14and gate driver IC 12 are made of silicon or other semiconductor wafersand mounted on the display panel, this is not restrictive. Needless tosay, they may be formed directly on the display panel 82 usinglow-temperature polysilicon technology or high-temperature polysilicontechnology.

Although it has been stated that pixels are of the three primary colorsof R, G, and B, this is not restrictive. They may be of three colors ofcyan, yellow, and magenta. They may be of two colors of B and yellow. Ofcourse, they may be monochromatic. Alternatively, they may be of sixcolors of R, G, B, cyan, yellow, and magenta or of five colors of R, G,B, cyan, and magenta. These are natural colors which provide an expandedcolor reproduction range, enabling good display. Thus, the EL displayapparatus according to the present invention is not limited to thosewhich provide color display using the three primary colors of R, G, andB.

Mainly three methods are available to colorize an organic EL displaypanel. One of them is a color conversion method. It suffices to form asingle layer of blue as a light-emitting layer. The remaining green andred colors needed for full color display can be produced from the bluecolor through color conversion. Thus, this method has the advantage ofeliminating the need to paint the R, G, and B colors separately andprepare organic EL materials for the R, G, and B colors. The colorconversion method does not lower yields unlike the multi-color paintingmethod. Any of the three methods can be applied to the EL display panelof the present invention.

Also, in addition to the three primary colors, white light-emittingpixels may be formed. The white light-emitting pixels can be created(formed or constructed) by laminating R, G, and B light-emittingstructures. A set of pixels consists of pixels for the three primarycolors RGB and a white light-emitting pixel 16W. Forming the whitelight-emitting pixels makes it easier to express peak brightness ofwhite, and thus possible to implement bright image display.

Even when using a set of pixels for the three primary colors RGB, it ispreferable to vary pixel electrode areas for the different colors. Ofcourse, an equal area may be used if luminous efficiencies of thedifferent colors as well as color purity are well balanced. However, ifone or more colors are poorly balanced, preferably the pixel electrodes(light-emitting areas) are adjusted. The electrode area for each colorcan be determined based on current density. That is, when white balanceis adjusted in a color temperature range of 7000 K (Kelvin) to 12000 K(both inclusive), difference between current densities of differentcolors should be within ±30%. More preferably, the difference should bewithin +15%. For example, if current densities are around 100 A/squaremeter, all the three primary colors should have a current density of 70A/square meter to 130 A/square meter (both inclusive) More preferably,all the three primary colors should have a current density of 85A/square meter to 115 A/square meter (both inclusive).

The EL element 15 is a self-luminous element. When light from thisself-luminous element enters a transistor serving as a switchingelement, a photoconductive phenomenon occurs. The photoconductivephenomenon is a phenomenon in which leakage (off-leakage) increases dueto photoexcitation when a switching element such as a transistor is off.

To deal with this problem, the present invention forms a shading filmunder the gate driver circuit 12 (source driver circuit 14 in somecases) and under the pixel transistor 11. The shading film is formed ofthin film of metal such as chromium and is from 50 nm to 150 nm thick(both inclusive). A thin film will provide a poor shading effect while athick film will cause irregularities, making it difficult to pattern thetransistor 11A1 in an upper layer.

In the case of the driver circuit 12 and the like, it is necessary toreduce penetration of light not only from the topside, but also from theunderside. This is because the photoconductive phenomenon will causemalfunctions. If cathode electrodes are made of metal films, the presentinvention also forms a cathode electrode on the surface of the driver 12and the like and uses it as a shading film.

However, if a cathode electrode is formed on the driver 12, electricfields from the cathode electrode may cause driver malfunctions or placethe cathode electrode and driver circuit in electrical contact. To dealwith this problem, the present invention forms at least one layer oforganic EL film, and preferably two or more layers, on the drivercircuit 12 simultaneously with the formation of organic EL film on thepixel electrode.

If a short circuit occurs between terminals of one or more transistors11 or between a transistor 11 and signal line in the pixel, the ELelement 15 may become a bright spot which remains illuminatedconstantly. The bright spot is visually conspicuous and must be turnedinto a black spot (turned off) The pixel 16 which corresponds to thebright spot is detected and the capacitor 19 is irradiated with laserlight to cause a short circuit across the capacitor. As a result, thecapacitor 19 can no longer hold electric charges, and thus thetransistor 11 a can be stopped from passing current. It is desirable toremove that part of a cathode film which will be irradiated with laserlight to prevent the laser irradiation from causing a short circuitbetween a terminal electrode of the capacitor 19 and the cathode film.

Flaws in a transistor 11 in the pixel 16 will affect the source driverIC 14 and the like. For example, if a source-drain (SD) short circuit452 occurs in the driver transistor 11 a in FIG. 45, a Vdd voltage ofthe panel is applied to the source driver IC 14. Thus, preferably thepower supply voltage of the source driver IC 14 is kept equal to orhigher than the power supply voltage Vdd of the panel. Preferably, thereference voltage used by the source driver IC 14 can be adjusted withan electronic regulator 451.

If an SD short circuit 452 occurs in the transistor 11 a, an excessivecurrent flows through the EL element 15. In other words, the EL element15 remains illuminated constantly (becomes a bright spot). The brightspot is conspicuous as a defect. For example, if a source-drain (SD)short circuit occurs in the transistor 11 a in FIG. 45, current flowsconstantly from the Vdd voltage to the EL element 15 (when thetransistor 11 d is on) regardless of the magnitude of gate (G) terminalvoltage of the transistor 11 a. Thus, a bright spot results.

On the other hand, if an SD short circuit occurs in the transistor 11 aand if the transistor 11 c is on, the Vdd voltage is applied to thesource signal line 18 and to the source driver circuit 14. If the powersupply voltage of the source driver circuit 14 is not higher than Vdd,voltage resistance may be exceeded, causing the source driver circuit 14to rupture. Thus, it is preferable that the power supply voltage of thesource driver circuit 14 is equal to or higher than the Vdd voltage (thehigher voltage of the panel).

An SD short circuit of the transistor 11 a may go beyond a point defectand lead to rupture of the source driver circuit of the panel. Also, thebright spot is conspicuous, which makes the panel defective. Thus, it isnecessary to turn the bright spot into a black spot by cutting thewiring which connects between the transistor 11 and EL element 15.Preferably an optical means such as laser light is used to cut thewiring.

A drive method according to the present invention will be describedbelow. As shown in FIG. 1, the gate signal line 17 a conducts when therow remains selected (since the transistor 11 in FIG. 1 is a P-channeltransistor, the gate signal line 17 a conducts when it is in low state)and the gate signal line 17 b conducts when the row remainsnon-selected.

Parasitic capacitance (not shown) is present in the source signal line18. The parasitic capacitance is caused by the capacitance at thejunction of the source signal line 18 and gate signal line 17, channelcapacitance of the transistors 11 b and 11 c, etc.

The time t required to change the current value of the source signalline 18 is given by t=CV/I, where C is stray capacitance, V is a voltageof the source signal line, and I is a current flowing through the sourcesignal line. Thus, if the current value can be increased ten fold, thetime required to change the current value can be reduced nearly tenfold.This also means that the current value can be changed to a predeterminedvalue even if the parasitic capacitance of the source signal line 18 isincreased tenfold. Thus, to apply a predetermined current value during ashort horizontal scanning period, it is useful to increase the currentvalue.

When input current is increased tenfold, output current is alsoincreased tenfold, resulting in a tenfold increase in the EL brightness.Thus, to obtain predetermined brightness, a light emission period isreduced tenfold by reducing the conduction period of the transistor 17 din FIG. 1 tenfold compared to a conventional conduction period.Incidentally, the tenfold increases/decreases are cited as an example tofacilitate understanding and are not meant to be restrictive.

Thus, in order to charge and discharge the parasitic capacitance of thesource signal line 18 sufficiently and program a predetermined currentvalue into the transistor 11 a of the pixel 16, it is necessary tooutput a relatively large current from the source driver circuit 14.However, when such a large current is passed through the source signalline 18, its current value is programmed into the pixel and a currentlarger than the predetermined current flows through the EL element 15.For example, if a 10 times larger current is programmed, naturally a 10times larger current flows through the EL element 15 and the EL element15 emits 10 times brighter light. To obtain predetermined emissionbrightness, the time during which the current flows through the ELelement 15 can be reduced tenfold. This way, the parasitic capacitancecan be charged/discharged sufficiently from the source signal line 18and the predetermined emission brightness can be obtained.

Incidentally, although it has been stated that a 10 times larger currentvalue is written into the pixel transistor 11 a (more precisely, theterminal voltage of the capacitor 19 is set) and that the conductionperiod of the EL element 15 is reduced to 1/10, this is only exemplary.In some cases, a 10 times larger current value may be written into thepixel transistor 11 a and the conduction period of the EL element 15 maybe reduced to 1/5. On the other hand, a 10 times larger current valuemay be written into the pixel transistor 11 a and the conduction periodof the EL element 15 may be halved.

The present invention is characterized in that the write current into apixel is set at a value other than a predetermined value and that acurrent is passed through the EL element 15 intermittently. For ease ofexplanation, it has been stated herein that an N times larger current iswritten into the pixel transistor 11 and the conduction period of the ELelement 15 is reduced to 1/N. However, this is not restrictive. Needlessto say, N1 times larger current may be written into the pixel transistor11 and the conduction period of the EL element 15 may be reduced to 1/N2(N1 and N2 are different from each other) In white raster display, it isassumed that average brightness over one field (frame) period of thedisplay screen 50 is B0. This drive method performs current (voltage)programming in such a way that the brightness B1 of each pixel 16 ishigher than the average brightness B0. Also, a non-display area 53appears during at least one field (frame) period. Thus, in the drivemethod according to the present invention, the average brightness overone field (frame) period is lower than B1.

Incidentally, the non-display area 52 and display area 53 are notnecessarily spaced equally. For example, they may appear at random(provided that the display period or non-display period makes up apredetermined value (constant ratio) as a whole). Also, display periodsmay vary among R, G, and B. That is, display periods of R, G, and B ornon-display period can be adjusted to a predetermined value (constantratio) in such a way as to obtain an optimum white balance.

To facilitate explanation of the drive method according to the presentinvention, it is assumed that “1/N” means reducing 1F (one field or oneframe) to 1/N. Needless to say, however, it takes time to select onepixel row and to program current values (normally, one horizontalscanning period (1 H)) and error may result depending on scanningconditions.

For example, the EL element 15 may be illuminated for 1/5 of a period byprogramming the pixel 16 with an N=10 times larger current. The ELelement 15 illuminates 10/5=2 times more brightly. It is also possibleto program an N=2 times larger current into the pixel 16 and illuminatethe EL element 15 for 1/4 of the period. The EL element 15 illuminates2/4=0.5 time more brightly. In short, the present invention achievesdisplay other than constant display (1/1, i.e., non-intermittentdisplay) by using a current other than an N=1 time current for currentprogramming. Also, the drive system turns off the current supplied tothe EL element 15, at least once during one frame (or one field) period.Also, the drive system at least achieves intermittent display byprogramming the pixel 16 with a current larger than a predeterminedvalue.

A problem with an organic (inorganic) EL display is that it uses adisplay method basically different from that of an CRT or other displaywhich presents an image as a set of displayed lines using an electrongun. That is, the EL display holds the current (voltage) written into apixel for 1F (one field or one frame) period. Thus, a problem is thatdisplaying moving pictures will result in blurred edges.

According to the present invention, current is passed through the ELelement 15 only for a period of 1F/N, but current is not passed duringthe remaining period (1F(N−1)/N). Let us consider a situation in whichthe drive system is implemented and one point on the screen is observed.In this display condition, image data display and black display(non-illumination) are repeated every 1F. That is, image data isdisplayed intermittently in the temporal sense. When moving picture dataare displayed intermittently, a good display condition is achievedwithout edge blur. In short, movie display close to that of a CRT can beachieved.

The drive method according to the present invention implementsintermittent display. However, the intermittent display can be achievedby simply turning on and off the transistor 11 d on a 1-H cycle.Consequently, a main clock of the circuit does not differ fromconventional ones, and thus there is no increase in the powerconsumption of the circuit. Liquid crystal display panels need an imagememory in order to achieve intermittent display. According to thepresent invention, image data is held in each pixel 16. Thus, thepresent invention requires no image memory for intermittent display.

The present invention controls the current passed through the EL element15 by simply turning on and off the switching transistor 11 d, thetransistor 11 e, and the like. That is, even if the current Iw flowingthrough the EL element 15 is turned off, the image data is held as it isin the capacitor 19. Thus, when the transistor 11 d is turned on thenext time, the current passed through the EL element 15 has the samevalue as the current flowing through the EL element 15 the previoustime. Even to achieve black insertion (intermittent display such asblack display), the present invention does not need to speed up the mainclock of the circuit. Also, it does not need to elongate a time axis,and thus requires no image memory. Besides, the EL element 15 respondsquickly, requiring a short time from application of current to lightemission. Thus, the present invention is suitable for movie display, andby using intermittent display, it can solve a problem with conventionaldata-holding display panels (liquid crystal display panels, EL displaypanels, etc.) in displaying moving pictures.

Furthermore, in a large display apparatus, if increased wiring length ofthe source signal line 18 results in increased parasitic capacitance inthe source signal line 18, this can be dealt with by increasing thevalue of N. When the value of programming current applied to the sourcesignal line 18 is increased N times, the conduction period of the gatesignal line 17 b (the transistor 11 d) can be set to 1F/N. This makes itpossible to apply the present invention to television sets, monitors,and other large display apparatus.

The drive method according to the present invention will be describedwith reference to drawings in more detail below. The parasiticcapacitance of the source signal line 18 is generated by the couplingcapacitance with adjacent source signal lines 18, buffer outputcapacitance of the source driver IC (circuit) 14, cross capacitancebetween the source signal line 18 and gate signal line 17, etc. Thisparasitic capacitance is normally 10 pF or larger. In the case ofvoltage driving, since voltage is applied to the source signal line 18from the source driver IC 14 at low impedance, more or less largeparasitic capacitance does not disturb driving.

However, in the case of current driving, especially image display at theblack level, the pixel capacitor 19 needs to be programmed with a minutecurrent of 20 nA or less. Thus, if parasitic capacitance larger than apredetermined value is generated, the parasitic capacitance cannot becharged and discharged during the time when one pixel row is programmed(normally within 1 H, but not limited to 1 H because two pixel rows maybe programmed simultaneously). If the parasitic capacitance cannot becharged and discharged within a period of 1 H, sufficient current cannotbe written into the pixel, resulting in inadequate resolution.

In the pixel configuration in FIG. 1, the programming current Iw flowsthrough the source signal line 18 during current programming as shown inFIG. 3(a). The current Iw flows through the transistor 11 a and voltageis set (programmed) in the capacitor 19 in such a way as to maintain thecurrent Iw. At this time, the transistor 1 d is open (off).

During a period when the current flows through the EL element 15, thetransistors 11 c and 11 b turn off and the transistor 11 d turns on asshown in FIG. 3(b). Specifically, a turn-off voltage (Vgh) is applied tothe gate signal line 17 a, turning off the transistors 11 b and 11 c. Onthe other hand, a turn-on voltage (Vgl) is applied to the gate signalline 17 b, turning on the transistor 11 d.

Suppose a current I1 is N times the current which should normally flow(a predetermined value), the current flowing through the EL element 15in FIG. 3(b) is also Iw. Thus, the EL element 15 emits light 10 timesmore brightly that a predetermined value. In other words, as shown inFIG. 12, the larger the magnification N, the higher the displaybrightness B of the pixel 16. Thus, the magnification N and thebrightness of the pixel 16 are proportional to each other.

If the transistor 11 d is kept on for a period 1/N the period duringwhich it is normally kept on (approximately 1F) and is kept off duringthe remaining period (N−1)/N, the average brightness over the 1F equalspredetermined brightness. This display condition closely resembles thedisplay condition under which a CRT is scanning a screen with anelectronic gun. The difference is that 1/N of the entire screenilluminates (where the entire screen is taken as 1) (in a CRT, whatilluminates is one pixel row—more precisely, one pixel).

According to the present invention, 1F/N of the image display area 53moves from top to bottom of the screen 50 as shown in FIG. 13(b).According to the present invention, current flows through the EL element15 only for the period of 1F/N, but current does not flow during theremaining period (1F(N−1) IN). Thus, the pixel is displayedintermittently. However, due to an afterimage, the entire screen appearsto be displayed uniformly to the human eye.

Incidentally, as shown in FIG. 13, the write pixel row 51 a isnon-illuminated 52 a. However, this is true only to the pixelconfigurations in FIGS. 1, 2, etc. In the pixel configuration of acurrent mirror shown in FIG. 38, etc., the write pixel row 51 a may beilluminated. However, description will be given herein citing mainly thepixel configuration in FIG. 1 for ease of explanation. A drive methodwhich involves driving a pixel intermittently by programming it with acurrent larger than the predetermined drive current Iw shown in FIGS.13, 16, etc. is referred to as N-fold pulse driving.

In this display condition, image data display and black display(non-illumination) are repeated every 1F. That is, image data isdisplayed at intervals (intermittently) in the temporal sense. Liquidcrystal display panels (EL display panels other than that of the presentinvention), which hold data in pixels for a period of 1F, cannot keep upwith changes in image data during movie display, resulting is blurredmoving pictures (edge blur of images). Since the present inventiondisplays images intermittently, it can achieve a good display conditionwithout edge blur of images. In short, movie display close to that of aCRT can be achieved.

Incidentally, to drive the pixel 16 as shown in FIG. 13, it is necessaryto be able to separately control the current programming period of thepixel 16 (in the configuration shown in FIG. 1, the period during whichthe turn-on voltage Vgl is applied to the gate signal line 17 a) and theperiod when the EL element 15 is under on/off control (in the pixelconfiguration shown in FIG. 1, the period during which the turn-onvoltage Vgl or turn-off voltage Vgh is applied to the gate signal line17 b). Thus, the gate signal line 17 a and gate signal line 17 b must beseparated.

For example, when only a single gate signal line 17 is laid from thegate driver circuit 12 to the pixel 16, the drive method according tothe present invention can not be implemented using a configuration inwhich logic (Vgh or Vgl) applied to the gate signal line 17 is appliedto the transistor 11 b and the logic applied to the gate signal line 17is converted (Vgh or Vgl) by an inverter and applied to the transistor11 d. Thus, the present invention requires a gate driver circuit 12 awhich operates the gate signal line 17 a and gate driver circuit 12 bwhich operates the gate signal line 17 b.

Besides, the drive method according to the present invention provides anon-illuminated display even with the pixel configuration shown in FIG.1 during periods other than the current programming period (1 H).

A timing chart of the drive method shown in FIG. 13 is illustrated inFIG. 14. The pixel configuration referred to in the present inventionand the like is the one shown in FIG. 1 unless otherwise stated. As canbe seen from FIG. 14, in each selected pixel row (the selection periodis designated as 1 H), when a turn-on voltage (Vgl) is applied to thegate signal line 17 a (see FIG. 14(a)), a turn-off voltage (Vgh) isapplied to the gate signal line 17 b (see FIG. 14(b)). During thisperiod, current does not flow through the EL element 15(non-illumination mode). In a non-selected pixel row, a turn-on voltage(Vgl) is applied to the gate signal line 17 b and a turn-off voltage(Vgh) is applied to the gate signal line 17 a. During this period,current flows through the EL element 15 (illumination mode). In theillumination mode, the EL element 15 illuminates at a brightness (NB) Ntimes the predetermined brightness and the illumination period is 1F/N.Thus, the average display brightness of the display panel over 1F isgiven by (N·B)×(1/N)=B (the predetermined brightness).

FIG. 15 shows an example in which operations shown in FIG. 14 areapplied to each pixel row. The figure shows voltage waveforms applied tothe gate signal lines 17. Waveforms of the turn-off voltage are denotedby Vgh (high level) while waveforms of the turn-on voltage are denotedby Vgl (low level). The subscripts such as (1) and (2) indicate selectedpixel row numbers.

In FIG. 15, a gate signal line 17 a(1) is selected (Vgl voltage) and aprogramming current flows through the source signal line 18 in thedirection from the transistor 11 a in the selected pixel row to thesource driver circuit 14. The programming current is N times larger thana predetermined value (for ease of explanation, it is assumed that N=10.Of course, since the predetermined value is a data current for use todisplay images, it is not a fixed value unless in the case of whiteraster display). Therefore, the capacitor 19 is programmed so that a 10times larger current will flow through the transistor 11 a. When thepixel row (1) is selected, in the pixel configuration shown in FIG. 1, aturn-off voltage (Vgh) is applied to the gate signal line 17 b(1) andcurrent does not flow through the EL element 15.

After 1 H, a gate signal line 17 a(2) is selected (Vgl voltage) and aprogramming current flows through the source signal line 18 in thedirection from the transistor 11 a in the selected pixel row to thesource driver circuit 14. The programming current is N times larger thana predetermined value (for ease of explanation, it is assumed thatN=10). Therefore, the capacitor 19 is programmed so that 10 times largercurrent will flow through the transistor 11 a. When the pixel row (2) isselected, in the pixel configuration shown in FIG. 1, a turn-off voltage(Vgh) is applied to the gate signal line 17 b(2) and current does notflow through the EL element 15. However, since a turn-off voltage (Vgh)is applied to the gate signal line 17 a(1) and a turn-on voltage (Vgl)is applied to the gate signal line 17 b(1) of the pixel row (1), the ELelement 15 illuminates.

After the next 1 H, a gate signal line 17 a(3) is selected, a turn-offvoltage (Vgh) is applied to the gate signal line 17 b(3), and currentdoes not flow through the EL element 15 in the pixel row (3). However,since a turn-off voltage (Vgh) is applied to the gate signal lines 17a(1) and (2) and a turn-on voltage (Vgl) is applied to the gate signallines 17 b(1) and

-   -   (2) in the pixel rows (1) and (2), the EL element 15        illuminates.

Through the above operation, images are displayed in sync with asynchronization signal of 1 H. However, with the drive method in FIG.15, a 10 times larger current flows through the EL element 15. Thus, thedisplay screen 50 is 10 times brighter. Of course, it goes withoutsaying that for display at a predetermined brightness in this state, theprogramming current can be reduced to 1/10. However, a 10 times smallercurrent will cause a shortage of write current due to parasiticcapacitance. Thus, the basic idea of the present invention is to use alarge current for programming, insert a non-display area 52, and therebyobtain a predetermined brightness.

Incidentally, the drive method according to the present invention causesa current larger than a predetermined current to flow through the ELelement 15, and thereby charges and discharges the parasitic capacitanceof the source signal line 18 sufficiently. That is, there is no need topass an N times larger current through the EL element 15. For example,it is conceivable to form a current path in parallel with the EL element15 (form a dummy EL element and use a shield film to prevent the dummyEL element from emitting light) and divide the flow of current betweenthe EL element 15 and the dummy EL element. For example, when a signalcurrent is 0.2 μA, a programming current is set to 2.2 μA and thecurrent of 2.2 μA is passed through the transistor 11 a. Then, thesignal current of 0.2 μA may be passed through the EL element 15 and 21Amay be passed through the dummy EL element, for example. That is, thedummy pixel row 271 in FIG. 27 remains selected constantly.Incidentally, the dummy pixel row is either kept from emitting light orhidden from view by a shield film or the like even if it emits light.

With the above configuration, by increasing the current passed throughthe source signal line 18N times, it is possible to pass an N timeslarger current through the driver transistor 11 a and pass a currentsufficiently smaller than the N times larger current through the ELelement 15. As shown in FIG. 5, this method allows the entire displayscreen 50 to be used as the image display area 53 without a non-displayarea 52.

FIG. 13(a) shows writing into the display screen 50. In FIG. 13(a),reference numeral 51 a denotes a write pixel row. A programming currentis supplied to the source signal line 18 from the source driver IC 14.In FIG. 13 and the like, there is one pixel row into which current iswritten during a period of 1 H, but this is not restrictive. The periodmay be 0.5 H or 2 Hs. Also, although it has been stated that aprogramming current is written into the source signal line 18, thepresent invention is not limited to current programming. The presentinvention may also use voltage programming (FIG. 46, etc.) which writesvoltage into the source signal line 18.

In FIG. 13(a), when the gate signal line 17 a is selected, the currentto be passed through the source signal line 18 is programmed into thetransistor 11 a. At this time, a turn-off voltage is applied to the gatesignal line 17 b, and current does not flow through the EL element 15.This is because when the transistor 11 d is on on the EL element 15, acapacitance component of the EL element 15 is visible from the sourcesignal line 18 and the capacitance prevents sufficient current frombeing programmed into the capacitor 19. Thus, to take the configurationshown in FIG. 1 as an example, the pixel row into which current iswritten is a non-illuminated area 52 as shown in FIG. 13(b).

Suppose an N times larger current is used for programming (it is assumedthat N=10 as described above), the screen becomes 10 times brighter.Thus, 90% of the display screen 50 can be constituted of thenon-illuminated area 52. Thus, for example, if the number of horizontalscanning lines in the screen display area is 220 (S=220) in compliancewith QCIF, 22 horizontal scanning lines can compose a display area 53while 220−22=198 horizontal scanning lines can compose a non-displayarea 52. Generally speaking, if the number of horizontal scanning lines(number of pixel rows) is denoted by S, S/N of the entire areaconstitutes a display area 53, which is illuminated N times morebrightly. Then, the display area 53 is scanned in the vertical directionof the screen. Thus, S (N−1)/N of the entire area is a non-illuminatedarea 52. The non-illuminated area presents a black display (isnon-luminous). Also, the non-luminous area 52 is produced by turning offthe transistor 11 d. Incidentally, although it has been stated that thedisplay area 53 is illuminated N times more brightly, naturally thevalue of N is adjusted by brightness adjustment and gamma adjustment.

In the above example, if a 10 times larger current is used forprogramming, the screen becomes 10 times brighter and 90% of the displayscreen 50 can be constituted of the non-illuminated area 52. However,this does not necessarily mean that R, G, and B pixels constitute thenon-illuminated area 52 in the same proportion. For example, 1/8 of theR pixels, 1/6 of the G pixels, and 1/10 of the B pixels may constitutethe non-illuminated area 52 with different colors making up differentproportions. It is also possible to allow the non-illuminated area 52(or illuminated area 53) to be adjusted separately among R, G, and B.For that, it is necessary to provide separate gate signal lines 17 b forR, G, and B. However, allowing R, G, and B to be adjusted separatelymakes it possible to adjust white balance, making it easy to adjustcolor balance for each gradation (see FIG. 41).

As shown in FIG. 13(b), pixel rows including the write pixel row 51 acompose a non-illuminated area 52 while an area of S/N (1F/N in thetemporal sense) above the write pixel row 51 a compose a display area 53(when write scans are performed from top to bottom of the screen. Whenthe screen is scanned from bottom to top, the areas change places).Regarding the display condition of the screen, a strip of the displayarea 53 moves from top to bottom of the screen.

In FIG. 13, one display area 53 moves from top to bottom of the screen.At a low frame rate, the movement of the display area 53 is recognizedvisually. It tends to be recognized easily especially when a user closeshis/her eyes or moves his/her head up and down.

To deal with this problem, the display area 53 can be divided into aplurality of parts as shown in FIG. 16. If the total area of the divideddisplay area is S (N−1)/N, the brightness is equal to the brightness inFIG. 13. Incidentally, there is no need to divide the display area 53equally. Also, there is no need to divide the non-display area 52equally.

Dividing the display area 53 reduces flickering of the screen. Thus, aflicker-free good image display can be achieved. Incidentally, thedisplay area 53 may be divided more finely. However, the more finely thedisplay area 53 is divided, the poorer the movie display performancebecomes.

FIG. 17 shows voltage waveforms of gate signal lines 17 and emissionbrightness of the EL element. As can be seen from FIG. 17, a period(1F/N) during which the gate signal line 17 b is set to Vgl is dividedinto a plurality of parts (K parts). That is, a period of 1F/(K·N)during which the gate signal line 17 b is set to Vgl repeats K times.This reduces flickering and implements image display at a low framerate. Preferably, the number of divisions is variable. For example, whenthe user presses a brightness adjustment switch or turns a brightnessadjustment knob, the value of K may be changed in response. Also, theuser may be allowed to adjust brightness. Alternatively, the value of Kmay be changed manually or automatically depending on images or data tobe displayed.

Incidentally, although it has been stated with reference to FIG. 17 andthe like that a period (1F/N) during which the gate signal line 17 b isset to Vgl is divided into a plurality of parts (K parts) and that aperiod of 1F/(KN) during which the gate signal line 17 b is set to Vglrepeats K times, this is not restrictive. A period of 1F/(KN) may berepeated L (L≠K) times. In other words, the present invention displaysthe display screen 50 by controlling the period (time) during whichcurrent is passed through the EL element 15. Thus, the idea of repeatingthe 1F/(K·N) period L (L≠K) times is included in the technical idea ofthe present invention. Also, by varying the value of L, the brightnessof the display screen 50 can be changed digitally. For example, there isa 50% change of brightness (contrast) between L=2 and L=3. Also, whendividing the image display area 53, the period when the gate signal line17 b is set to Vg1 does not necessarily need to be divided equally.

In the example described above, the display screen 50 is turned on andoff (illuminated and non-illuminated) as the current delivered to the ELelement 15 is switched on and off. That is, approximately equal currentis passed through the transistor 11 a multiple times using electriccharges held in the capacitor 19. The present invention is not limitedto this. For example, the display screen 50 may be turned on and off(illuminated and non-illuminated) by charging and discharging thecapacitor 19.

FIG. 18 shows voltage waveforms applied to gate signal lines 17 toachieve the image display condition shown in FIG. 16. FIG. 18 differsfrom FIG. 15 in the operation of the gate signal line 17 b. The gatesignal line 17 b is turned on and off (Vgl and Vgh) as many times asthere are screen divisions. FIG. 18 is the same as FIG. 15 in otherrespects, and thus description thereof will be omitted.

Since black display on EL display apparatus corresponds to completenon-illumination, contrast does not lower unlike in the case ofintermittent display on liquid crystal display panels. Also, with theconfigurations in FIGS. 1, 2, 32, 43, and 117, intermittent display canbe achieved by simply turning on and off the transistor 11 d. With theconfigurations in FIGS. 38, 51, and 115, intermittent display can beachieved by simply turning on and off the transistor element 11 e. InFIG. 113, intermittent display can be achieved by controlling theswitching circuit 1131. In FIG. 114, intermittent display can beachieved by turning on and off the transistor 11 g. This is becauseimage data is stored in the capacitor 19 (the number of gradations isinfinite because analog values are used). That is, the image data isheld in each pixel 16 for a period of 1F. Whether to deliver a currentwhich corresponds to the stored image data to the EL element 15 iscontrolled by controlling the transistors 11 d and 11 e.

Thus, the drive method described above is not limited to acurrent-driven type and can be applied to a voltage-driven type as well.That is, in a configuration in which the current passed through the ELelement 15 is stored in each pixel, intermittent driving is implementedby switching on and off the current path between the driver transistor11 and EL element 15.

It is important to maintain terminal voltage of the capacitor 19 inorder to reduce flickering and power consumption. This is because if theterminal voltage of the capacitor 19 changes (charge/discharge) duringone field (frame) period, flickering occurs when the screen brightnesschanges and the frame rate lowers. The current passed through the ELelement 15 by the transistor 11 a must be higher than 65%. Morespecifically, if the initial current written into the pixel 16 andpassed through the EL element 15 is taken as 100%, the current passedthrough the EL element 15 just before it is written into the pixel 16 inthe next frame (field) must not fall below 65%.

With the pixel configuration shown in FIG. 1, there is no difference inthe number of transistors 11 in a single pixel between when anintermittent display is created and when an intermittent display is notcreated. That is, leaving the pixel configuration as it is, propercurrent programming is achieved by removing the effect of parasiticcapacitance of the source signal line 18. Besides, movie display closeto that of a CRT is achieved.

Also, since the operation clock of the gate driver circuit 12 issignificantly slower than the operation clock of the source drivercircuit 14, there is no need to upgrade the main clock of the circuit.Besides, the value of N can be changed easily.

Incidentally, the image display direction (image writing direction) maybe from top to bottom of the screen in the first field (frame), and frombottom to top of the screen in the second field (frame). That is, anupward direction and downward direction may be repeated alternately.

Alternatively, it is possible to use a downward direction in the firstfield (frame), turn the entire screen into black display (non-display)once, and use an upward direction in the second field (frame). It isalso possible to turn the entire screen into black display (non-display)once.

Incidentally, although top-to-bottom and bottom-to-top writingdirections on the screen are used in the drive method described above,this is not restrictive. It is also possible to fix the writingdirection on the screen to a top-to-bottom direction or bottom-to-topdirection and move the non-display area 52 from top to bottom in thefirst field, and from bottom to top in the second field. Alternatively,it is possible to divide a frame into three fields and assign the firstfield to R, the second field to G, and the third field to B so thatthree fields compose a single frame. It is also possible to display R,G, and B in turns by switching among them every horizontal scanningperiod (1 H) (see FIGS. 125 to 132 and their description). The itemsmentioned above also apply to other examples of the present invention.

The non-display area 52 need not be totally non-illuminated. Weak lightemission or dim image display will not be a problem in practical use. Itshould be regarded to be an area which has a lower display brightnessthan the image display area 53. Also, the non-display area 52 may be anarea which does not display one or two colors out of R, G, and B. Also,it may be an area which displays one or two colors among R, G, and B atlow brightness.

Basically, if the brightness of the display area 53 is kept at apredetermined value, the larger the display area 53, the brighter thedisplay screen 50. For example, when the brightness of the image displayarea 53 is 100 (nt), if the percentage of the display screen 50accounted for by the display area 53 changes from 10% to 20%, thebrightness of the screen is doubled. Thus, by varying the proportion ofthe display area 53 in the entire screen 50, it is possible to vary thedisplay brightness of the screen. The display brightness of the screen50 is proportional to the ratio of the display area 53 to the screen 50.

The size of the display area 53 can be specified freely by controllingdata pulses (ST2) sent to the shift register circuit 61. Also, byvarying the input timing and period of the data pulses, it is possibleto switch between the display condition shown in FIG. 16 and displaycondition shown in FIG. 13. Increasing the number of data pulses in oneIF period makes the screen 50 brighter and decreasing it makes thescreen 50 dimmer. Also, continuous application of the data pulses bringson the display condition shown in FIG. 13 while intermittent applicationof the data pulses brings on the display condition shown in FIG. 16.

FIG. 19(a) shows a brightness adjustment scheme used when the displayarea 53 is continuous as in FIG. 13. The display brightness of thescreen 50 in FIG. 19(a 1) is the brightest, the display brightness ofthe screen 50 in FIG. 19(a 2) is the second brightest, and displaybrightness of the screen 50 in FIG. 19(a 3) is the dimmest. FIG. 19(a)is most suitable for movie display.

Changes from FIG. 19(a 1) to FIG. 19(a 3) (or vice versa) can beachieved easily by controlling the shift register circuit 61 and thelike of the gate driver circuit 12 as described above. In this case,there is no need to vary the Vdd voltage in FIG. 1. That is, thebrightness of the screen 50 can be varied without changing the powersupply voltage. Also, in the process of change from FIG. 19(a 1) to FIG.19(a 3), the gamma characteristics of the screen do not change at all.Thus, the contrast and gradation characteristics of the display screenare maintained regardless of the brightness of the screen 50. This is aneffective feature of the present invention.

In brightness adjustment of a conventional screen, low brightness of thescreen 50 results in poor gradation performance. That is, even if 64gradations can be displayed in a high-brightness display, in most cases,less than half the gradations can be displayed in a low-brightnessdisplay. In contrast, the drive method according to the presentinvention does not depend on the display brightness of the screen andcan display up to 64 gradations, which is the highest.

FIG. 19(b) shows a brightness adjustment scheme used when the displayareas 53 are scattered as in FIG. 16. The display brightness of thescreen 50 in FIG. 19(b 1) is the brightest, the display brightness ofthe screen 50 in FIG. 19(b 2) is the second brightest, and displaybrightness of the screen 50 in FIG. 19(b 3) is the dimmest. Changes fromFIG. 19(b 1) to FIG. 19(b 3) (or vice versa) can be achieved easily bycontrolling the shift register circuit 61 of the gate driver circuit 12and the like as described above. By scattering the display areas 53 asshown in FIG. 19(b), it is possible to eliminate flickering even at alow frame rate.

To eliminate flickering at an even lower frame rate, the display areas53 can be scattered more finely as shown in FIG. 19(c). However, thislowers movie display performance. Thus, the drive method in FIG. 19(a)is suitable for moving pictures. The drive method in FIG. 19(c) issuitable when it is desired to reduce power consumption by displayingstill pictures. Switching from FIG. 19(a) to FIG. 19(c) can be doneeasily by controlling the shift register circuit 61.

Mainly, N=two times, N=4 times, etc. are used in the above example.Needless to say, however, the present invention is not limited tointegral multiples. It is not limited to a value equal to or larger thanN=two, either. For example, less than half the screen 50 may be anon-display area 52 at a certain time point. A predetermined brightnesscan be achieved if a current Iw 5/4 a predetermined value is used forcurrent programming and the EL element is illuminated for 4/5 of 1F.

The present invention is not limited to the above. For example, acurrent Iw 10/4 a predetermined value may be used for currentprogramming to illuminate the EL element for 4/5 of 1F. In this case,the EL element illuminates at twice a predetermined brightness.Alternatively, a current Iw 5/4 a predetermined value may used forcurrent programming to illuminate the EL element for 2/5 of 1F. In thiscase, the EL element illuminates at 1/2 the predetermined brightness.Also, a current Iw 5/4 a predetermined value may be used for currentprogramming to illuminate the EL element for 1/1 of 1F. In this case,the EL element illuminates at 5/4 the predetermined brightness.

Thus, the present invention controls the brightness of the displayscreen by controlling the magnitude of programming current andillumination period IF. Also, by illuminating the EL element for aperiod shorter than the period of 1F, the present invention can insert anon-display area 52, and thereby improve movie display performance. Byilluminating the EL element constantly for the period of 1F, the presentinvention can display a bright screen.

If pixel size is A square mm and predetermined brightness of whiteraster display is B (nt), preferably programming current I (IA)(programming current outputted from the source driver circuit 14) or thecurrent written into the pixel satisfies:(A×B)/20≦I≦(A×B)

This provides good light emission efficiency and solves a shortage ofwrite current.

More preferably, the programming current I (μA) falls within the range:(A×B)/10≦I≦(A×B)

FIG. 20 is an explanatory diagram illustrating another example ofincreasing the current flowing through a source signal line 18. Thismethod selects a plurality of pixel rows simultaneously, charges anddischarges parasitic capacitance and the like of the source signal line18 using the total current flowing through the plurality of pixel rows,and thereby eases a shortage of write current greatly. Since a pluralityof pixel rows are selected simultaneously, drive current per pixel canbe reduced. Thus, it is possible to reduce the current flowing throughthe EL element 15. For ease of explanation, it is assumed that N=10 (thecurrent passed through the source signal line 18 is increased tenfold).

According to the invention described with reference to FIG. 20, M pixelrows are selected simultaneously. A current N times larger than apredetermined current is applied to the source signal line 18 from thesource driver IC 14. A current N/M times larger than the current passedthrough the EL element 15 is programmed into each pixel. As an example,to illuminate the EL element 15 at a predetermined emission brightness,current is passed through the EL element 15 for a duration of M/N theduration of one frame (one field) (M/N is used for ease of explanationand is not meant to be restrictive. As described earlier, it can bespecified freely depending on the brightness of the screen 50). Thismakes it possible to charge and discharge parasitic capacitance of thesource signal line 18 sufficiently, resulting in a sufficient resolutionat the predetermined emission brightness.

Current is passed through the EL element 15 only for a period M/N theframe (field) period, but current is not passed during the remainingperiod (1F(N−1) M/N). In this display condition, image data display andblack display (non-illumination) are repeated every 1F. That is, imagedata is displayed at intervals (intermittently) in the temporal sense.This achieves a good display condition without edge blur of images.Also, since the source signal line 18 is driven by an N times largercurrent, it is not affected by parasitic capacitance. Thus, this methodcan accommodate high-resolution display panels.

FIG. 21 is an explanatory diagram illustrating drive waveforms used toimplement the drive method shown in FIG. 20. Waveforms of the turn-offvoltage are denoted by Vgh (H level) while waveforms of the turn-onvoltage are denoted by (L level). The subscripts (such as (1), (2), and(3)) indicate pixel row numbers. Incidentally, the number of rows is 220in the case of a QCIF display panel, and 480 in the case of a VGAdisplay panel.

In FIG. 21, a gate signal line 17 a(1) is selected (Vgl voltage) and aprogramming current flows through the source signal line 18 in thedirection from the transistor 11 a in the selected pixel row to thesource driver circuit 14. For ease of explanation, it is assumed herethat the write pixel row 51 a is the (1)-th pixel row.

The programming current flowing through the source signal line 18 is Ntimes larger than a predetermined value (for ease of explanation, it isassumed that N=10. Of course, since the predetermined value is a datacurrent for use to display images, it is not a fixed value unless in thecase of white raster display). It is also assumed that five pixel rowsare selected simultaneously (M=5). Therefore, ideally the capacitor 19of one pixel is programmed so that a twice (N/M=10/5=2) larger currentwill flow through the transistor 11 a.

When the write pixel row is the (1)-th pixel row, the gate signal lines17 a(1), (2), (3), (4), and (5) are selected as shown in FIG. 21. Thatis, the switching transistors 11 b and the transistors 11 c in the pixelrows (1), (2), (3), (4), and (5) are on. Also, the gate signal lines 17b are 180 degrees out of phase with the gate signal lines 17 a. Thus,the switching transistors 11 d in the pixel rows (1), (2), (3), (4), and(5) are off and current does not flow through the EL elements 15 in thecorresponding pixel rows. That is, the EL elements 15 are innon-illumination mode 52.

Ideally, the transistors 11 a in the five pixels deliver a current ofIw×2 each to the source signal line 18 (i.e., a current ofIw×2×N=Iw×2×5=Iw×10 flows through the source signal line 18. Thus, if apredetermined voltage Iw flows when the N-fold pulse driving accordingto the present invention is not used, a current 10 times larger than Iwflows through the source signal line 18).

Through the above operation (drive method), the capacitor 19 of eachpixel 16 is programmed with a twice larger current. For ease ofunderstanding, it is assumed here that the transistors 11 a have equalcharacteristics (Vt and S value) Since five pixel rows are selectedsimultaneously (M=5), five driver transistors 11 a operate. That is,10/5=2 times larger current flows through the transistor 11 a per pixel.The total programming current of the five transistors 11 a flows throughthe source signal line 18. For example, if a current conventionallywritten into the write pixel row 51 a is Iw, a current of Iw×10 ispassed through the source signal line 18. The write pixel rows 51 b intowhich image data is written later than the write pixel row (1) areauxiliary pixel rows used to increase the amount of current delivered tothe source signal line 18. However, there is no problem because regularimage data is written into the write pixel rows 51 b later.

Thus, the four pixel rows 51 b provide the same display as the pixel row51 a during a period of 1 H. Consequently, at least the write pixel row51 a and the pixel rows 51 b selected to increase current are innon-display mode 52. However, in the pixel configuration of a currentmirror, such as shown in FIG. 38, or pixel configuration for voltageprogramming, the pixel rows may be in display mode.

After 1 H, the gate signal line 17 a (1) becomes deselected and aturn-on voltage (Vgl) is applied to the gate signal line 17 b. At thesame time, the gate signal line 17 a(6) is selected (Vgl voltage) and aprogramming current flows through the source signal line 18 in thedirection from the transistor 11 a in the selected pixel row (6) to thesource driver circuit 14. Through this operation, regular image data isheld in the pixel row (1).

After the next 1 H, the gate signal line 17 a(2) becomes deselected anda turn-on voltage (Vgl) is applied to the gate signal line 17 b. At thesame time, the gate signal line 17 a(7) is selected (Vgl voltage) and aprogramming current flows through the source signal line 18 in thedirection from the transistor 11 a in the selected pixel row (7) to thesource driver circuit 14. Through this operation, regular image data isheld in the pixel row (2). The entire screen is redrawn as it is scannedby shifting pixel rows one by one through the above operations.

With the drive method in FIG. 20, since each pixel is programmed with atwice larger current, ideally the emission brightness of the EL element15 of each pixel is two times higher. Thus, the brightness of thedisplay screen is twice higher than a predetermined value. To equalizethis brightness with the predetermined brightness, an area whichincludes the write pixel rows 51 and which is half as large as thedisplay screen 50 can be turned into a non-display area 52 asillustrated in FIG. 16.

As is the case with FIG. 13, when one display area 53 moves from top tobottom of the screen as shown in FIG. 20, the movement of the displayarea 53 is recognized visually if a low frame rate is used. It tends tobe recognized easily especially when the user closes his/her eyes ormoves his/her head up and down.

To deal with this problem, the display area 53 can be divided into aplurality of parts as illustrated in FIG. 22. If the total area of thedivided non-display area 52 is S(N−1)/N, the brightness is equal to thebrightness of the undivided display area.

FIG. 23 shows voltage waveforms applied to gate signal lines 17. FIG. 21differs from FIG. 23 basically in the operation of the gate signal line17 b. The gate signal line 17 b is turned on and off (Vgl and Vgh) asmany times as there are screen divisions. FIG. 23 is the same as FIG. 21in other respects, and thus description thereof will be omitted.

As described above, dividing the display area 53 reduces flickering ofthe screen. Thus, a flicker-free good image display can be achieved.Incidentally, the display area 53 may be divided more finely. The morefinely the display area 53 is divided, the less flickering occurs. Sincethe EL element 15 is highly responsive, even if it is turned on and offat intervals shorter than 5 μsec, there is no lowering of the displaybrightness.

With the drive method according to the present invention, the EL element15 can be turned on and off by turning on and off a signal applied tothe gate signal line 17 b. Thus, the drive method according to thepresent invention can perform control using a low frequency on the orderof KHz. Also, it does not need an image memory or the like in order toinsert a black screen (insert a non-display area 52). Thus, the drivecircuit or method according to the present invention can be implementedat low costs.

FIG. 24 shows a case in which two pixel rows are selectedsimultaneously. It was found that on a display panel formed bylow-temperature polysilicon technology, a method in which two pixel rowswere selected simultaneously provided uniform display on a practicallevel. Probably this is because driver transistors 11 a in adjacentpixels had very similar characteristics. In laser annealing, goodresults were obtained when laser stripes were irradiated in parallelwith the source signal line 18.

This is because that part of a semiconductor film which is annealedsimultaneously has uniform characteristics. That is, the semiconductorfilm is created uniformly within an irradiation range of laser stripesand the Vt and mobility of the transistors which use the semiconductorfilm are almost uniform. Thus, if a striped laser shot is moved inparallel with the source signal line 18, pixels (a pixel column, i.e.,pixels arranged vertically on the screen) along the source signal line18 take on almost equal characteristics. Therefore, if a plurality ofpixel rows are turned on simultaneously for current programming, thecurrent obtained by dividing the programming current by the number ofselected pixels are programmed almost uniformly into the pixels Thismakes it possible to program a current close to a target value andachieve uniform display. Thus, the direction of a laser shot and thedrive method described with reference to FIG. 24 and the like have asynergistic effect.

As described above, if the direction of a laser shot is made to coincideapproximately with the direction of the source signal line 18 (see FIG.7), the characteristics of the pixel transistors 11 a arrangedvertically become almost uniform, making it possible to do propercurrent programming (even if the characteristics of the pixeltransistors 11 a arranged horizontally are not uniform). The aboveoperation is performed in sync with 1 H (one horizontal scanning period)by shifting selected pixel rows one by one or by shifting two or moreselected pixel rows at once.

Incidentally, as described with reference to FIG. 8, the direction ofthe laser shot does not always need to be parallel with the direction ofthe source signal line 18. This is because even if the laser shot isdirected at angles to the source signal line 18, pixel transistors 11 aplaced along one source signal line 18 can be made to take on almostequal characteristics. Thus, directing a laser shot in parallel with thesource signal line 18 means bringing a pixel vertically adjacent to anarbitrary pixel along the source signal line 18 into a laser irradiationrange. Besides, a source signal line 18 generally constitutes wiringwhich transmits programming current or voltage used as a video signal.

Incidentally, in the examples of the present invention a write pixel rowis shifted every 1 H, but this is not restrictive. Pixel rows may beshifted every 2 Hs (two pixel rows at a time). Also, more than two pixelrows may be shifted at a time. Also, pixel rows may be shifted atdesired time intervals or every second pixel may be shifted.

The shifting interval may be varied according to locations on thescreen. For example, the shifting interval may be decreased in themiddle of the screen, and increased at the top and bottom of the screen.For example, a pixel row may be shifted at intervals of 200 μsec. in themiddle of the screen 50, and at intervals of 100 μsec. at the top andbottom of the screen 50. This increases emission brightness in themiddle of the screen 50 and decreases it around the perimeters (at thetop and bottom of the screen 50)). Needless to say, the shiftinginterval is varied smoothly among the top, middle, and bottom of thescreen 50 to avoid brightness contours.

Incidentally, the reference voltage of the source driver circuit 14 maybe varied with the scanning location on the screen 50 (see FIG. 146,etc.). For example, a reference current of 10 μA is used in the middleof the screen 50 and a reference current of 5 μA is used at the top ofthe screen 50. Varying a reference current in this way corresponding toa location in the screen 50, increases emission brightness in the middleof the screen 50 and decreases it around the perimeters (at the top andbottom of the screen 50)). Needless to say, the reference current isvaried smoothly among the top, middle, and bottom of the screen 50 toavoid brightness contours.

Also, it goes without saying that images may be displayed by combining adrive method which varies the pixel-row shifting interval with thelocation on the screen and a drive method which varies the referencevoltage with the location on the screen 50.

The shifting interval may be varied on a frame-by-frame basis. Also, itis not strictly necessary to select consecutive pixel rows. For example,every second pixel row may be selected.

Specifically, a possible drive method involves selecting the first andthird pixel rows in the first horizontal scanning period, the second andfourth pixel rows in the second horizontal scanning period, the thirdand fifth pixel rows in the third horizontal scanning period, and thefourth and sixth pixel rows in the fourth horizontal scanning period. Ofcourse, a drive method which involves selecting the first, third, andfifth pixel rows in the first horizontal scanning period also belongs tothe technical category of the present invention. Also, one in every fewpixel rows may be selected.

Incidentally, the combination of the direction of a laser shot andselection of multiple pixel rows is not limited to the pixelconfigurations in FIGS. 1, 2, and 32, but it is also applicable to othercurrent-driven pixel configurations such as the current-mirror pixelconfigurations in FIGS. 38, 42, 50, etc. Also, it can be applied tovoltage-driven pixel configurations in FIGS. 43, 51, 54, 46, etc. Thisis because as long as transistors in upper and lower parts of the pixelhave equal characteristics, current programming can be performedproperly using the voltage value applied to the same source signal line18.

In FIG. 24, when the write pixel row is the (1)-th pixel row, the gatesignal lines 17 a(1) and (2) are selected (see FIG. 25). That is, theswitching transistors 11 b and the transistors 11 c in the pixel rows(1) and (2) are on. Thus, at least the switching transistors 11 d in thepixel rows (1) and (2) are off and current does not flow through the ELelements 15 in the corresponding pixel rows. That is, the EL elements 15are in non-illumination mode 52. Incidentally, in FIG. 24, the displayarea 53 is divided into five parts to reduce flickering.

Ideally, the transistors 1 a in the two pixel rows deliver a current ofIw×5 each to the source signal line 18 (when N=10. Since K=2, a currentof Iw×K×5=Iw×10 flows through the source signal line 18). Then, thecapacitor 19 of each pixel 16 is programmed with a 5 times largercurrent.

Since two pixel rows are selected simultaneously (K=2), two drivertransistors 11 a operate. That is, 10/2=5 times larger current flowsthrough the transistor 11 a per pixel. The total programming current ofthe two transistors 1 a flows through the source signal line 18.

For example, if the current written into the write pixel row 51 a is Id,a current of Iw×10 is passed through the source signal line 18. There isno problem because regular image data is written into the write pixelrow 51 b later. The pixel row 51 b provides the same display as thepixel row 51 a during a period of 1 H. Consequently, at least the writepixel row 51 a and the pixel row 51 b selected to increase current arein non-display mode 52.

After the next 1 H, the gate signal line 17 a(1) becomes deselected anda turn-on voltage (Vgl) is applied to the gate signal line 17 b. At thesame time, the gate signal line 17 a(3) is selected (Vgl voltage) and aprogramming current flows through the source signal line 18 in thedirection from the transistor 11 a in the selected pixel row (3) to thesource driver circuit 14. Through this operation, regular image data isheld in the pixel row (1).

After the next 1 H, the gate signal line 17 a(2) becomes deselected anda turn-on voltage (Vgl) is applied to the gate signal line 17 b. At thesame time, the gate signal line 17 a(4) is selected (Vgl voltage) and aprogramming current flows through the source signal line 18 in thedirection from the transistor 11 a in the selected pixel row (4) to thesource driver circuit 14. Through this operation, regular image data isheld in the pixel row (2). The entire screen is redrawn as it is scannedby shifting pixel rows one by one through the above operations (ofcourse, two or more pixel rows may be shifted simultaneously. Forexample, in the case of pseudo-interlaced driving, two pixel rows willbe shifted at a time. Also, from the viewpoint of image display, thesame image may be written into two or more pixel rows).

As in the case of FIG. 16, with the drive method in FIG. 24, since eachpixel is programmed with a five times larger current (voltage), ideallythe emission brightness of the EL element 15 is five times higher. Thus,the brightness of the display area 53 is five times higher than apredetermined value. To equalize this brightness with the predeterminedbrightness, an area which includes the write pixel rows 51 and which is1/5 the display screen 50 can be turned into a non-display area 52.

As shown in FIG. 27, two write pixel rows 51 (51 a and 51 b) areselected in sequence from the upper side to the lower side of the screen50 (see also FIG. 26. Pixels 16 a and 16 b are selected in FIG. 26).However, at the bottom of the screen, there does not exist 51 b althoughthe write pixel row 51 a exists. That is, there is only one pixel row tobe selected. Thus, the current applied to the source signal line 18 isall written into the write pixel row 51 a. Consequently, twice as largea current as usual is written into the write pixel row 51 a.

To deal with this problem, the present invention forms (places) a dummypixel row 271 at the bottom of the screen 50, as shown in FIG. 27(b).Thus, after the pixel row at the bottom of the screen 50 is selected,the final pixel row of the screen 50 and the dummy pixel row 271 areselected. Consequently, a prescribed current is written into the writepixel row in FIG. 27(b).

Incidentally, although the dummy pixel row 271 is illustrated as beingadjacent to the top end or bottom end of the display screen 50, this isnot restrictive. It may be formed at a location away from the displayscreen 50. Besides, the dummy pixel row 271 does not need to contain aswitching transistor 11 d or EL element 15 such as those shown inFIG. 1. This reduces the size of the dummy pixel row 271.

FIG. 28 shows a mechanism of how the state shown in FIG. 27(b) takesplace. As can be seen from FIG. 28, after the pixel 16 c at the bottomof the screen 50 is selected, the final pixel row (dummy pixel row) 271of the screen 50 is selected. The dummy pixel row 271 is placed outsidethe screen 50. That is, the dummy pixel row (dummy pixel) 271 does notilluminate, is not illuminated, or is hidden even if illuminated. Forexample, contact holes between the pixel electrode 105 and transistor 11are eliminated, no EL film is formed on the dummy pixel row 271, or thelike. Also, an insulating film may be formed on the pixel electrode 105of the dummy pixel row 271.

Although it has been stated with reference to FIG. 27 that the dummypixel (row) 271 is provided (formed or placed) at the bottom of thescreen 50, this is not restrictive. For example when the screen isscanned from bottom to top (inverse scanning) as shown in FIG. 29(a), adummy pixel row 271 should also be formed at the top of the screen 50 asshown in FIG. 29(b). That is, dummy pixel rows 271 are formed (placed)both at the top and bottom of the screen 50. This configurationaccommodates in verses canning of the screen as well. Two pixel rows areselected simultaneously in the example described above.

The present invention is not limited to this. For example, five pixelrows may be selected simultaneously (see FIG. 23). When five pixel rowsare selected simultaneously, four dummy pixel rows 271 should be formed.That is, the number of dummy pixel rows 271 equals the number of pixelrows selected simultaneously minus one. However, this is true only whenthe selected pixel rows are shifted one by one. When two or more pixelrows are shifted at a time, (M−1)×L dummy pixel rows should be formed,where M is the number of pixels selected and L is the number of pixelrows shifted at a time.

The dummy pixel row configuration or dummy pixel row driving accordingto the present invention uses one or more dummy pixel rows. Of course,it is preferable to use the dummy pixel row driving and N-fold pulsedriving in combination.

In the drive method which selects two or more pixel rows at a time, thelarger the number of pixel rows selected simultaneously, the moredifficult it becomes to absorb variations in the characteristics of thetransistors 11 a. However, the current programmed into one pixelincreases with decreases in the number M of pixel rows selectedsimultaneously, resulting in a large current flowing through the ELelement 15, which in turn makes the EL element 15 prone to degradation.

FIG. 30 shows how to solve this problem. The basic concept behind FIG.30 is to use a method of selecting a plurality of pixel rowssimultaneously during 1/2 H (1/2 of a horizontal scanning period) asdescribed with reference to FIGS. 22 and 29 and to use a method ofselecting one pixel row in the latter 1/2 H (1/2 of the horizontalscanning period) as described with reference to FIGS. 5 and 13. Thiscombination makes it possible to absorb variations in thecharacteristics of the transistors 11 a and achieve high speed anduniform surfaces. Incidentally, although the period of 1/2 H is used forease of understanding, this is not restrictive. The first period may be1/4 H and the second period may be 3/4 H.

Referring to FIG. 30, for ease of understanding, it is assumed that fivepixel rows are selected simultaneously in the first period and that onepixel row is selected in the second period. First, as shown in FIG. 30(a1), in the first period (first 1/2 H), five pixel rows are selectedsimultaneously. This operation has been described with reference to FIG.22, and thus description thereof will be omitted. As an example, it isassumed that the current passed through the source signal line 18 is 25times as large as a predetermined value. Thus, the transistor 11 a inthe pixel 16 (in the pixel configuration in FIG. 1) is programmed with afive times larger current (25/5 pixel rows=5). Since the current is 25times larger, the parasitic capacitance generated in the source signalline 18 and the like is charged and discharged in an extremely shortperiod. Consequently, the potential of the source signal line 18 reachesa target potential in a short period of time and the terminal voltage ofthe capacitor 19 of each pixel 16 is programmed to pass a 25 timeslarger current. The 25 times larger current is applied in the first 1/2H (1/2 of the horizontal scanning period).

Naturally, since the same image data is written into the five writepixel rows, the transistors 11 d in the five write pixel rows are turnedoff in order not to display the image. Thus, the display condition is asshown in FIG. 30(a 2).

In the next 1/2 H period, one pixel is selected for current (voltage)programming. The condition is as shown in FIG. 30(b 1). Current(voltage) programming is performed so as to pass a five times largercurrent through the write pixel row 51 a as in the first period. Equalcurrent is passed in FIG. 30(a 1) and FIG. 30(b 1) to reach a targetcurrent more quickly by decreasing the changes in the terminal voltageof the programmed capacitor 19.

Specifically, in FIG. 30(a 1), current is passed through a plurality ofpixels, approaching an approximate target value quickly. In this firststage, since a plurality of transistors 11 a are programmed, variationsin the transistors cause error with respect to the target value. In thesecond stage, only a pixel row where data will be written and held isselected and complete programming is performed by changing the value ofcurrent from the approximate target value to a predetermined targetvalue.

Incidentally, scanning of the non-illuminated area 52 from top to bottomof the screen and scanning of the write pixel rows 51 a from top tobottom of the screen are performed in the same manner as in examples inFIG. 13 and the like, and thus description thereof will be omitted.

FIG. 31 shows drive waveforms used to implement the drive method shownin FIG. 30. As can be seen from FIG. 31, 1 H (one horizontal scanningperiod) consists of two phases. An ISEL signal is used to switch betweenthe two phases. The ISEL signal is illustrated in FIG. 31.

First, the ISEL signal will be described. The driver circuit 14 whichperforms operations shown in FIG. 30 comprises a current output circuitA and current output circuit B. Each of the current output circuitsconsists of a D/A circuit which converts 8-bit gradation data fromdigital to analog, an operation amplifier, etc. In the example in FIG.30, the current output circuit A is configured to output 25 times largercurrent. On the other hand, the current output circuit B is configuredto output 5 times larger current. Outputs from the current outputcircuit A and current output circuit B are controlled by a switchcircuit formed (placed) in a current output section through the ISELsignals and are applied to the source signal line 18. Such currentoutput circuits are placed on each source signal line 18.

When the ISEL signal is low, the current output circuit A which outputs25 times larger current is selected and current from the source signalline 18 is absorbed by the source driver IC 14 (more precisely, thecurrent is absorbed by the current output circuit A formed in the sourcedriver IC 14). The magnification (such as ×25 or ×5) of the current fromthe current output circuits can be adjusted easily using a plurality ofresisters and an analog switch.

As shown in FIG. 30, when the write pixel row is the (1)-th pixel row(see the 1 H column in FIG. 30), the gate signal lines 17 a(1), (2),(3), (4), and (5) are selected (in the case of configuration shown inFIG. 1). That is, the switching transistors 11 b and the transistors 11c in the pixel rows (1), (2), (3), (4), and (5) are on. Besides, sinceISEL is low, the current output circuit A which outputs 25 times largercurrent is selected and connected to the source signal line 18. Also, aturn-off voltage (Vgh) is applied to the gate signal line 17 b. Thus,the switching transistors 11 d in the pixel rows (1), (2), (3), (4), and(5) are off and current does not flow through the EL elements 15 in thecorresponding pixel rows. That is, the EL elements 15 are innon-illumination mode 52.

Ideally, the transistors 11 a in the five pixels deliver a current ofIw×2 each to the source signal line 18. Then, the capacitor 19 of eachpixel 16 is programmed with a five times larger current. For ease ofunderstanding, it is assumed here that the transistors have equalcharacteristics (Vt and S value).

Since five pixel rows are selected simultaneously (K=5), five drivertransistors 11 a operate. That is, 25/5=5 times larger current flowsthrough the transistor 11 a per pixel. The total programming current ofthe five transistors 11 a flows through the source signal line 18. Forexample, if the current written into the write pixel row 51 a by aconventional drive method is Iw, a current of Iw×25 is passed throughthe source signal line 18. The write pixel rows 51 b into which imagedata is written later than the write pixel row (1) are auxiliary pixelrows used to increase the amount of current delivered to the sourcesignal line 18. However, there is no problem because regular image datais written into the write pixel rows 51 b later.

Thus, the pixel rows 51 b provide the same display as the pixel row 51 aduring a period of 1 H. Consequently, at least the write pixel row 51 aand the pixel rows 51 b selected to increase current are in non-displaymode 52.

In the next 1/2 H period (1/2 of the horizontal scanning period), onlythe write pixel row 51 a is selected. That is, only the (1)-th pixel rowis selected. As can be seen from FIG. 31, a turn-on voltage (Vgl) isapplied only to the gate signal line 17 a(1) and a turn-off voltage(Vgh) is applied to the gate signal lines 17 a(2), (3), (4), and (5).Thus, the transistor 11 a in the pixel row (1) is in operation(supplying current to the source signal line 18), but the switchingtransistors 11 b and the transistors 11 c in the pixel rows (2), (3),(4), and (5) are off. That is, they are non-selected.

Besides, since ISEL is high, the current output circuit B which outputs5 times larger current is selected and connected to the source signalline 18. Also, a turn-off voltage (Vgh) is applied to the gate signalline 17 b, which is in the same state as during the first 1/2 H. Thus,the switching transistors 11 d in the pixel rows (1), (2), (3), (4), and(5) are off and current does not flow through the EL elements 15 in thecorresponding pixel rows. That is, the EL elements 15 are innon-illumination mode 52.

Thus, each transistor 11 a in the pixel row (1) deliver a current ofIw×5 to the source signal line 18. Then, the capacitor 19 in each pixelrow (1) is programmed with a 5 times larger current.

In the next horizontal scanning period, the write pixel row shifts byone. That is, the pixel row (2) becomes the current write pixel row.During the first 1/2 H period, when the write pixel row is the (2)-thpixel row, the gate signal lines 17 a(2), (3), (4), and (5) and (6) areselected. That is, the switching transistors 11 b and the transistors 11c in the pixel rows (2), (3), (4), (5), and (6) are on. Besides, sinceISEL is low, the current output circuit A which outputs 25 times largercurrent is selected and connected to the source signal line 18. Also, aturn-off voltage (Vgh) is applied to the gate signal line 17 b.

Thus, the switching transistors 11 d in the pixel rows (2), (3), (4),(5), and (6) are off and current does not flow through the EL elements15 in the corresponding pixel rows. That is, the EL elements 15 are innon-illumination mode 52. On the other hand, since Vgl voltage isapplied to the gate signal line 17 b(1) of the pixel row (1), thetransistor 11 d is on and the EL element 15 in the pixel row (1)illuminates.

Since five pixel rows are selected simultaneously (K=5), five drivertransistors 11 a operate. That is, 25/5=5 times larger current flowsthrough the transistor 11 a per pixel. The total programming current ofthe five transistors 11 a flows through the source signal line 18.

In the next 1/2 H period (1/2 of the horizontal scanning period), onlythe write pixel row 51 a is selected. That is, only the (2)-th pixel rowis selected. As can be seen from FIG. 31, a turn-on voltage (Vgl) isapplied only to the gate signal line 17 a(2) and a turn-off voltage(Vgh) is applied to the gate signal lines 17 a (3), (4), (5), and (6).

Thus, the transistors 11 a in the pixel rows (1) and (2) are inoperation (the pixel row (1) supplies current to the EL element 15 andthe pixel row (2) supplies current to the source signal line 18), butthe switching transistors 11 b and the transistors 11 c in the pixelrows (3), (4), (5), and (6) are off. That is, they are non-selected.

Besides, since ISEL is high, the current output circuit B which outputs5 times larger current is selected and the current output circuit 1222 bis connected to the source signal line 18. Also, a turn-off voltage(Vgh) is applied to the gate signal line 17 b, which is in the samestate as during the first 1/2 H. Thus, the switching transistors 11 d inthe pixel rows (2), (3), (4), (5), and (6) are off and current does notflow through the EL elements 15 in the corresponding pixel rows. Thatis, the EL elements 15 are in non-illumination mode 52.

Thus, each transistor 11 a in the pixel row (1) deliver a current ofIw×5 to the source signal line 18. Then, the capacitor 19 in each pixelrow (1) is programmed with a 5 times larger current. The entire screenis drawn as the above operations are performed in sequence.

The drive method described with reference to FIG. 30 selects G pixelrows (G is 2 or larger) in the first period and does programming in sucha way as to pass N times larger current through each pixel row. In thesecond period, the drive method selects B pixel rows (B is smaller thanG, but not smaller than 1) and does programming in such a way as to passan N times larger current through the pixels.

Another scheme is also available. It selects G pixel rows (G is 2 orlarger) in the first period and does programming in such a way that thetotal current in all the pixel rows will be an N times larger current.In the second period, this scheme selects B pixel rows (Bis smaller thanG, but not smaller than 1) and does programming in such a way that thetotal current in the selected pixel rows (the current in the one pixelrow if one pixel row is selected) will be an N times larger current. Forexample, in FIG. 30(a 1), five pixel rows are selected simultaneouslyand a twice larger current is passed through the transistor 11 a in eachpixel. Thus, 5×2=10 times larger current flows through the source signalline 18. In the second period, one pixel row is selected in FIG. 30(b1). A 10 times larger current is passed through the transistor 11 a inthis pixel.

Incidentally, although a plurality of pixel rows are selectedsimultaneously in a period of 1/2 H and a single pixel row is selectedin a period of 1/2 H in FIG. 31, this is not restrictive. A plurality ofpixel rows may be selected simultaneously in a period of 1/4 H and asingle pixel row may be selected in a period of 3/4 H. Also, the sum ofthe period in which a plurality of pixel rows are selectedsimultaneously and the period in which a single pixel row is selected isnot limited to 1 H. For example, the total period may be 2 Hs or 1.5 Hs.

In FIG. 30, it is also possible to select two pixel rows simultaneouslyin the second period after selecting five pixel rows simultaneously inthe first 1/2 H. This can also achieve a practically acceptable imagedisplay.

In FIG. 30, pixel rows are selected in two stages—five pixel rows areselected simultaneously in the first 1/2 H period and a single pixel rowis selected in the second 1/2 H period, but this is not restrictive. Forexample, it is also possible to select five pixel rows simultaneously inthe first stage, select two of the five pixel rows in the second stage,and finally select one pixel row in the third stage. In short, imagedata may be written into pixel rows in two or more stages.

In the example described above, pixel rows are selected one by one andprogrammed with current, or two or more pixel rows are selected at atime and programmed with current. However, the present invention is notlimited to this. It is also possible to use a combination of the twomethods according to image data: the method of selecting pixel rows oneby one and programming them with current and the method of selecting twoor more pixel rows at a time and programming them with current.

Now, interlaced driving according to the present invention will bedescribed below. FIG. 133 shows a configuration of the display panelaccording to the present invention which performs the interlaceddriving. In FIG. 133, the gate signal lines 17 a of odd-numbered pixelrows are connected to a gate driver circuit 12 a 1. The gate signallines 17 a of even-numbered pixel rows are connected to a gate drivercircuit 12 a 2. On the other hand, the gate signal lines 17 b of theodd-numbered pixel rows are connected to a gate driver circuit 12 b 1.The gate signal lines 17 b of the even-numbered pixel rows are connectedto a gate driver circuit 12 b 2.

Thus, through operation (control) of the gate driver circuit 12 a 1,image data in the odd-numbered pixel rows are rewritten in sequence. Inthe odd-numbered pixel rows, illumination and non-illumination of the ELelements are controlled through operation (control) of the gate drivercircuit 12 b 1. Also, through operation (control) of the gate drivercircuit 12 a 2, image data in the even-numbered pixel rows are rewrittenin sequence. In the even-numbered pixel rows, illumination andnon-illumination of the EL elements are controlled through operation(control) of the gate driver circuit 12 b 2.

FIG. 134(a) shows operating state in the first field of the displaypanel. FIG. 134(b) shows operating state in the second field of thedisplay panel. Incidentally, for ease of understanding, it is assumedthat one frame consists of two fields. In FIG. 134, the oblique hatchingwhich marks the gate driver circuits 12 indicates that the gate drivercircuits 12 are not taking part in data scanning operation.Specifically, in the first field in FIG. 134(a), the gate driver circuit12 a 1 is operating for write control of programming current and thegate driver circuit 12 b 2 is operating for illumination control of theEL element 15. In the second field in FIG. 134(b), the gate drivercircuit 12 a 2 is operating for write control of programming current andthe gate driver circuit 12 b 1 is operating for illumination control ofthe EL element 15. The above operations are repeated within the frame.

FIG. 135 shows image display status in the first field. FIG. 135(a)illustrates write pixel rows (locations of odd-numbered pixel rowsprogrammed with current (voltage) The location of the write pixel row isshifted in sequence: FIG. 135(a 1)→(a 2)→(a 3). In the first field,odd-numbered pixel rows are rewritten in sequence (image data in theeven-numbered pixel rows are maintained). FIG. 135(b) illustratesdisplay status of odd-numbered pixel rows. Incidentally, FIG. 135(b)illustrates only odd-numbered pixel rows. Even-numbered pixel rows areillustrated in FIG. 135(c). As can be seen from FIG. 135(b), the ELelements 15 of the pixels in the odd-numbered pixel rows arenon-illuminated. On the other hand, the even-numbered pixel rows arescanned in both display area 53 and non-display area 52 as shown in FIG.135(c) (N-fold pulse driving).

FIG. 136 shows image display status in the second field. FIG. 136(a)illustrates write pixel rows (locations of odd-numbered pixel rowsprogrammed with current (voltage) The location of the write pixel row isshifted in sequence: FIG. 136(a 1)→(a 2)→(a 3). In the second field,even-numbered pixel rows are rewritten in sequence (image data in theodd-numbered pixel rows are maintained). FIG. 136(b) illustrates displaystatus of odd-numbered pixel rows. Incidentally, FIG. 136(b) illustratesonly odd-numbered pixel rows. Even-numbered pixel rows are illustratedin FIG. 136(c). As can be seen from FIG. 136(b), the EL elements 15 ofthe pixels in the even-numbered pixel rows are non-illuminated. On theother hand, the odd-numbered pixel rows are scanned in both display area53 and non-display area 52 as shown in FIG. 136(c) (N-fold pulsedriving).

In this way, interlaced driving can be implemented easily on an ELdisplay panel. Also, N-fold pulse driving eliminates shortages of writecurrent and blurred moving pictures. Besides, current (voltage)programming and illumination of EL elements 15 can be controlled easilyand circuits can be implemented easily.

Incidentally, the drive method according to the present invention is notlimited to those shown in FIGS. 135 and 136. For example, a drive methodshown in FIG. 137 is also available. Whereas in FIGS. 135 and 136, theodd-numbered pixel rows or even-numbered pixel rows being programmedbelong to a non-display area 52 (non-illumination or black display), theexample in FIG. 137 involves synchronizing the gate driver circuits 12 b1 and 12 b 2 which control illumination of the EL elements 15. Needlessto say, however, the write pixel row 51 being programmed with current(voltage) belongs to a non-display area (there is no need for this inthe case of the current-mirror pixel configuration in FIG. 38). In FIG.137, since illumination control is common to the odd-numbered pixel rowsand even-numbered pixel rows, there is no need to provide two gatedriver circuits: 12 b 1 and 12 b 2. The gate driver circuit 12 b alonecan perform illumination control.

The drive method in FIG. 137 uses illumination control for bothodd-numbered pixel rows and even-numbered pixel rows. However, thepresent invention is not limited to this. FIG. 138 shows an example inwhich illumination control varies between odd-numbered pixel rows andeven-numbered pixel rows. In FIG. 138, the illumination mode (displayarea 53 and non-display area 52) of odd-numbered pixel rows andillumination mode of even-numbered pixel rows have opposite patterns.Thus, display area 53 and non-display area 52 have the same size.However, this is not restrictive.

Also, in FIGS. 136 and 135, it is not strictly necessary that all thepixel rows in the odd-numbered pixel rows or even-numbered pixel rowsshould be non-illuminated.

In the above example, the drive method programs pixel rows with current(voltage) one at a time. However, the drive method according to thepresent invention is not limited to this. Needless to say, two pixelrows (a plurality of pixel rows) may be programmed with current(voltage) simultaneously as shown in FIG. 139 (see also FIG. 27 and itsdescription) FIG. 139(a) shows an example concerning odd-numbered fieldswhile FIG. 139(b) shows an example concerning an even-numbered fields.In odd-numbered fields, combinations of two pixel rows (1, 2), (3, 4),(5, 6), (7, 8), (9, 10), (11, 12), . . . , (n, n+1) are selected insequence and programmed with current (where n is an integer not smallerthan 1). In even-numbered fields, combinations of two pixel rows (2, 3),(4, 5), (6, 7), (8, 9), (10, 11), (12, 13), . . . , (n+1, n+2) areselected in sequence and programmed with current (where n is an integernot smaller than 1).

By selecting a plurality of pixel rows in each field and programmingthem with current, it is possible to increase the current to be passedthrough the source signal line 18, and thus write black properly. Also,by shifting combinations of pixel rows selected in odd-numbered fieldsand even-numbered fields at least by one pixel row, it is possible toincrease the resolution of images.

Although in the example in FIG. 139, two pixel rows are selected in eachfield, this is not restrictive and three pixel rows may be selected. Inthis case, the three pixel rows selected in both odd-numbered fields andeven-numbered fields may be shifted by either one pixel row or two pixelrows. Also, four or more pixel rows may be selected in each field.Besides, as shown in FIGS. 125 to 132, one frame may be composed ofthree or more field.

Also, although in the example in FIG. 139, two pixel rows are selectedsimultaneously, this is not restrictive. It is possible to divide 1 Hinto a first 1/2 H and second 1/2 H and perform current programming inodd-numbered fields by selecting the first pixel row in the first 1/2 Hof the first 1 H and selecting the second pixel row in the second 1/2 Hof the first 1 H, selecting the third pixel row in the first 1/2 H ofthe second 1 H and selecting the fourth pixel row in the second 1/2 H ofthe second 1 H, selecting the fifth pixel row in the first 1/2 H of thethird 1 H and selecting the sixth pixel row in the second 1/2 H of thethird 1 H, and so on.

In even-numbered fields, current programming can be performed byselecting the second pixel row in the first 1/2 H of the first 1 H andselecting the third pixel row in the second 1/2 H of the first 1 H,selecting the fourth pixel row in the first 1/2 H of the second 1 H andselecting the fifth pixel row in the second 1/2 H of the second 1 H,selecting the sixth pixel row in the first 1/2 H of the third 1 H andselecting the seventh pixel row in the second 1/2 H of the third 1 H,and so on.

Again, although in the above example, two pixel rows are selected ineach field, this is not restrictive and three pixel rows may beselected. In this case, the three pixel rows selected in bothodd-numbered fields and even-numbered fields may be shifted by eitherone pixel row or two pixel rows. Also, four pixel rows may be selectedin each field.

The N-fold pulse driving method according to the present invention usesthe same waveform for the gate signal lines 17 b of different pixel rowsand applies current by shifting the pixel rows at 1 H intervals. The useof such scanning makes it possible to shift illuminating pixel rows insequence with the illumination duration of the EL elements 15 fixed to1F/N. It is easy to shift pixel rows in this way while using the samewaveform for the gate signal lines 17 b of the pixel rows. It can bedone by simply controlling data ST1 and ST2 applied to the shiftregister circuits 61 a and 61 b in FIG. 6. For example, if Vgl is outputto the gate signal line 17 b when input ST1 is low and Vgh is output tothe gate signal line 17 b when input ST1 is high, ST2 applied to theshift register circuit 17 b can be set low for a period of 1F/N and sethigh for the remaining period. Then, inputted ST2 can be shifted using aclock CLK2 synchronized with 1 H.

Incidentally, the EL elements 15 must be turned on and off at intervalsof 0.5 msec or longer. Short intervals will lead to insufficient blackdisplay due to persistence of vision, resulting in blurred images andmaking it look as if the resolution has lowered. This also represents adisplay state of a data holding display. However, increasing the on/offintervals to 100 msec will cause flickering. Thus, the on/off intervalsof the EL elements must be not shorter than 0.5 μsec and not longer than100 msec. More preferably, the on/off intervals should be from 2 msec to30 msec (both inclusive). Even more preferably, the on/off intervalsshould be from 3 msec to 20 msec (both inclusive).

As also described above, an undivided black screen 52 achieves goodmovie display, but makes flickering of the screen more noticeable. Thus,it is desirable to divide the black insert into multiple parts. However,too many divisions will cause moving pictures to blur. The number ofdivisions should be from 1 to 8 (both inclusive). More preferably, itshould be from 1 to 5 (both inclusive).

Incidentally, it is preferable that the number of divisions of a blackscreen can be varied between still pictures and moving pictures. WhenN=4, 75% is occupied by a black screen and 25% is occupied by imagedisplay. When the number of divisions is 1, a strip of black displaywhich makes up 75% is scanned vertically. When the number of divisionsis 3, three blocks are scanned, where each block consists of a blackscreen which makes up 25% and a display screen which makes up 25/3percent. The number of divisions is increased for still pictures anddecreased for moving pictures. The switching can be done eitherautomatically according to input images (detection of moving pictures)or manually by the user. Alternatively, the switching can be doneaccording to input outlet such as video on the display apparatus.

For example, for wallpaper display or an input screen on a cell phone,the number of divisions should be 10 or more (in extreme cases, thedisplay may be turned on and off every 1 H). When displaying movingpictures in NTSC format, the number of divisions should be from 1 to 5(both inclusive). Preferably, the number of divisions can be switched inthree or more steps; for example, 0, 2, 4, 8 divisions, and so onPreferably, the ratio of the black screen to the entire display screenshould be from 0.2 to 0.9 (from 1.2 to 9 in terms of N) both inclusivewhen the area of the entire screen is taken as 1. More preferably, theratio should be from 0.25 to 0.6 (from 1.25 to 6 in terms of N) bothinclusive. If the ratio is 0.20 or less, movie display is not improvedmuch. When the ratio is 0.9 or more, the display part becomes bright andits vertical movements become liable to be recognized visually.

Also, preferably, the number of frames per second is from 10 to 100 (10Hz to 100 Hz) both inclusive. More preferably, it is from 12 to 65 (12Hz to 65 Hz) both inclusive. When the number of frames is small,flickering of the screen becomes conspicuous while too large a number offrames makes writing from the source driver circuit 14 and the likedifficult, resulting in deterioration of resolution.

Needless to say, the above items also apply to the pixel configurationsfor current programming in FIG. 38 and the like as well as to the pixelconfigurations for voltage programming in FIGS. 43, 51, 54, and thelike. This can be accomplished through on/off control of the transistor11 d in FIG. 38, transistor 11 d in FIG. 43, and transistor 11 e in FIG.51. In this way, by turning on and off the wiring which delivers currentto the EL elements 15, the N-fold pulse driving according to the presentinvention can be implemented easily.

Also, the gate signal line 17 b may be set to Vgl for a period of 1F/Nanytime during the period of 1F (not limited to 1F. Any unit time willdo). This is because a predetermined brightness is obtained by turningoff the EL element 15 for a predetermined period out of a unit time.However, it is preferable to set the gate signal line 17 b to Vgl andilluminate the EL element 15 immediately after the current programmingperiod (1 H). This will reduce the effect of retention characteristicsof the capacitor 19 in FIG. 1.

Also, preferably the number of screen divisions is configured to bevariable. For example, when the user presses a brightness adjustmentswitch or turns a brightness adjustment knob, the value of K may bechanged in response. Alternatively, the value of K may be changedmanually or automatically depending on images or data to be displayed.

In this way, the mechanism for changing the value of K (the number ofdivisions of the image display part 53) can be implemented easily. Thiscan be achieved by simply making the time to change ST (when to set STlow during 1F) adjustable or variable.

Incidentally, although it has been stated with reference to FIG. 16 andthe like that a period (1F/N) during which the gate signal line 17 b isset to Vgl is divided into a plurality of parts (K parts) and that aperiod of 1F/(K·N) during which the gate signal line 17 b is set to Vglrepeats K times, this is not restrictive. A period of 1F/(KN) may berepeated L (L≠K) times. In other words, the present invention displaysthe display screen 50 by controlling the period (time) during whichcurrent is passed through the EL element 15. Thus, the idea of repeatingthe 1F/(K·N) period L (L≠K) times is included in the technical idea ofthe present invention. Also, by varying the value of L, the brightnessof the display screen 50 can be changed digitally. For example, there isa 50% change of brightness (contrast) between L=2 and L=3. The controldescribed here is also applicable to other examples of the presentinvention (of course, it is applicable to what is described laterherein). These are also included in the N-fold pulse driving accordingto the present invention.

The above examples involve placing (forming) the transistor 11 d servingas a switching element between the EL element 15 and driver transistor11 a and turning on and off the screen 50 by controlling the transistor11 d. This drive method eliminates shortages of write current in blackdisplay condition during current programming and thereby achieves properresolution or black display. That is, in current programming, it isimportant to achieve proper black display. The drive method describednext achieves proper black display by resetting the driver transistor 11a. This example will be described below with reference to FIG. 32.

The pixel configuration in FIG. 32 is basically the same as the oneshown in FIG. 1. With the pixel configuration in FIG. 32, a programmedIw current flows through the EL element 15, illuminating the EL element15. By being programmed, the driver transistor 11 a retains a capabilityto pass current. The drive system shown in FIG. 32 resets (turns off)the transistor 11 a using this capability to pass current. Hereinafter,this drive system will be referred to as reset driving.

To implement reset driving using the pixel configuration shown in FIG.1, the transistors 11 b and 11 c must be able to be switched on and offindependently of each other. Specifically, as illustrated in FIG. 32, itis necessary to be able to independently control the gate signal line 17a (gate signal line WR) used for on/off control of the transistor 11 band the gate signal line 17 c (gate signal line EL) used for on/offcontrol of the transistor 11 c. The gate signal lines 17 a and 17 c canbe controlled using two independent shift registers 61 as illustrated inFIG. 6.

Preferably, the drive voltage should be varied between the gate signalline 17 a which drives the transistor 11 b and the gate signal line 17 bwhich drives the transistor 11 d (when the pixel configuration in FIG. 1is used). The amplitude value (difference between turn-on voltage andturn-off voltage) of the gate signal line 17 a should be smaller thanthe amplitude value of the gate signal line 17 b.

Too large an amplitude value of the gate signal line 17 will increasepenetration voltage between the gate signal line 17 and pixel 16,resulting in an insufficient black level. The amplitude of the gatesignal line 17 a can be controlled by controlling the time when thepotential of the source signal line 18 is not applied (or is applied(during selection)) to the pixel 16. Since changes in the potential ofthe source signal line 18 are small, the amplitude value of the gatesignal line 17 a can be made small.

On the other hand, the gate signal line 17 b is used for on/off controlof EL. Thus, its amplitude value becomes large. For this, output voltageis varied between the shift register circuits 61 a and 61 b. If thepixel is constructed of P-channel transistors, approximately equal Vgh(turn-off voltage) is used for the shift register circuits 61 a and 61 bwhile Vgl (turn-on voltage) of the shift register circuit 61 a is madelower than Vgl (turn-on voltage) of the shift register circuit 61 b.

Reset driving will be described below with reference to FIG. 33. FIG. 33is a diagram illustrating a principle of reset driving. First, asillustrated in FIG. 33(a), the transistors 11 c and 11 d are turned offand the transistor 11 b is turned on. As a result, the drain (D)terminal and gate (G) terminal of the driver transistor 11 a areshort-circuited, allowing a current Ib to flow. Generally, thetransistor 11 a has been programmed with current in the previous field(frame). In this state, as the transistor 11 d is turned off and thetransistor 11 b is turned on, the drive current Ib flows through thegate (G) terminal of the transistor 11 a. Consequently, the gate (G)terminal and drain (D) terminal of the transistor 11 a have the samepotential, resetting the transistor 11 a (to a state in which no currentflows).

Incidentally, before the operation in FIG. 33(a), it is preferable toturn off the transistors 11 b and 11 c, turn on the transistor 11 d, andpass current through the driver transistor 11 a. Preferably, thisoperation should be completed in a minimum time. Otherwise, there is afear that a current will flow through the EL element 15, illuminatingthe EL element 15, and thereby lowering display contrast. Preferably,the operating time here is from 0.1% to 10% of 1 H (one horizontalscanning period) both inclusive. More preferably, it is from 0.2% to 2%or from 0.2 μsec to 5 μsec (both inclusive). Also, this operation (theoperation to be performed before the operation in FIG. 33(a)) may beperformed on all the pixels 16 of the screen at once. This operationwill lower the drain (D) terminal voltage of the driver transistor 11 a,making it possible to pass the current Ib smoothly in the state shown inFIG. 33(a). Incidentally, the above items also apply to other resetdriving according to the present invention.

As the operation time of FIG. 33(a) becomes longer, a larger Ib currenttends to flow, reducing the terminal voltage of the capacitor 19. Thus,the operation time of FIG. 33(a) should be fixed. It has been shownexperimentally and analytically that preferably the operation time inFIG. 33(a) is from 1 H to 5 Hs (both inclusive).

Preferably, this period should be varied among R, G, and B pixels. Thisis because EL material varies among different colors and rising voltagevaries among different EL materials. Optimum periods suitable for ELmaterials should be specified separately for the R, G, and B pixels.Although it has been stated that the period should be from 1 H to 5 Hs(both inclusive) in this example, it goes without saying that the periodmay be 5 Hs or longer in the case of a drive system which mainlyconcerns black insertion (writing of a black screen). Incidentally, thelonger the period, the better the black display condition of pixels.

A state shown in FIG. 33(b) occurs during a period of 1 H to 5 Hs (bothinclusive) after the state in FIG. 33(a). FIG. 33(b) shows a state inwhich the transistors 11 c and 11 b are on and the transistor 11 d isoff. This is a state in which current programming is being performed, asdescribed earlier. Specifically, a programming current Iw is output (orabsorbed) from the source driver circuit 14 and passed through thedriver transistor 11 a. The potential of the gate (G) terminal of thedriver transistor 11 a is set so that the programming current Iw flows(the set potential is held in the capacitor 19).

If the programming current Iw is 0 A, the transistor 11 a is held in thestate in FIG. 33(a) in which it does not pass current, and thus a properblack display is achieved. Also, when performing current programming forwhite display in FIG. 33(b), the current programming is started fromoffset voltage of completely black display even if there are variationsin the characteristics of driver transistors in pixels. Thus, the timerequired to reach a target current value becomes uniform according togradations. This eliminates gradation errors due to variations in thecharacteristics of the transistors 11 a, making it possible to achieveproper image display.

After the programming in FIG. 33(b), the transistors 11 b and 11 c areturned off in sequence and the transistor 11 d is turned on to deliverthe programming current Iw (=Ie) to the EL element 15 from the drivertransistor 11 a, and thereby illuminate the EL element 15. What is shownin FIG. 33(c) has already been described with reference to FIG. 1 andthe like, and thus detailed description thereof will be omitted.

The drive system (reset driving) described with reference to FIG. 33consists of a first operation of disconnecting the driver transistor 11a from the EL element 15 (so that no current flows) and shorting betweenthe drain (D) terminal and gate (G) terminal of the driver transistor(or between the source (S) terminal and gate (G) terminal, or generallyspeaking, between two terminals including the gate (G) terminal of thedriver transistor) and a second operation of programming the drivertransistor with current (voltage) after the first operation. At leastthe second operation is performed after the first operation.Incidentally, for reset driving, the transistors 11 b and 11 c must beable to be controlled independently as shown in FIG. 32.

In image display mode (if instantaneous changes can be observed), thepixel row to be programmed with current is reset (black display mode)and is programmed with current after 1H (also in black display modebecause the transistor 11 d is off) Next, current is supplied to the ELelement 15 and the pixel row illuminates at a predetermined brightness(at the programmed current) That is, the pixel row of black displaymoves from top to bottom of the screen and it should look as if theimage were rewritten at the location where the pixel row passed by.

Incidentally, although it has been stated that current programming isperformed 1 H after a reset, this period may be approximately 5 Hs orshorter. This is because it takes a relatively long time for the resetin FIG. 33(a) to be completed. If this period is 5 Hs, five pixel rowswill be displayed in black (six pixel rows including the pixel row goingthrough current programming).

Also, the number of pixel rows which are reset at a time is not limitedto one, and two or more pixel rows may be reset at a time. It is alsopossible to reset and scan two or more pixel rows at a time byoverlapping some of them. For example, if four pixel rows are reset at atime, pixel rows (1), (2), (3), and (4) are reset in the firsthorizontal scanning period (1 unit), pixel rows (3), (4), (5), and (6)are reset in the second horizontal scanning period, pixel rows (5), (6),(7), and (8) are reset in the third horizontal scanning period, andpixel rows (7), (8), (9), and (10) are reset in the fourth horizontalscanning period. Incidentally the drive operations in FIGS. 33(b) and33(c) are naturally carried out in sync with the drive operation in FIG.33(a).

Needless to say, the drive operation in (c) of FIG. 33(b) may beperformed after resetting all the pixels in the screen simultaneously orduring scanning. Also, it goes without saying that pixel rows may bereset (at intervals of one or more pixel rows) in interlaced drivingmode (scanning at intervals of one or more pixel rows). Also, pixel rowsmay be reset at random. The reset driving according to the presentinvention involves operating pixel rows (i.e., controlling the verticaldirection of the screen). However, the concept of reset driving does notlimit control directions to the pixel row direction. For example, itgoes without saying that reset driving may be performed in the directionof pixel columns.

Incidentally, the reset driving in FIG. 33 can achieve better imagedisplay if combined with the N-fold pulse driving according to thepresent invention or with interlaced driving. Particularly, theconfiguration in FIG. 22 can easily implement intermittent N/K-foldpulse driving (this driving method provides two or more illuminatedareas in a screen and can be implemented easily by turning on and offthe transistor 11 d by controlling the gate signal line 17 b: this hasbeen described earlier), and thus can achieve proper image displaywithout flickering.

Needless to say, more excellent image display can be achieved bycombining with precharge driving or the like described later. Thus, itgoes without saying that reset driving can be performed in combinationwith other examples according to the present invention.

FIG. 34 is a block diagram of a display apparatus which implement resetdriving. The gate driver circuit 12 a controls the gate signal line 17 aand gate signal line 17 b in FIG. 32. By the application of on/offvoltages to the gate signal line 17 a, the transistor 11 b is turned onand off. Also, by the application of on/off voltages to the gate signalline 17 b, the transistor 11 d is turned on and off. The gate drivercircuit 12 b controls the gate signal line 17 c in FIG. 32. By theapplication of on/off voltages to the gate signal line 17 c, thetransistor 11 c is turned on and off.

Thus, the gate signal line 17 a is controlled by the gate driver circuit12 a while the gate signal line 17 c is controlled by the gate drivercircuit 12 b. This makes it possible to freely specify the time to turnon the transistor 11 b and reset the driver transistor 11 a as well asthe time to turn on the transistor 111 c and program the drivertransistor 11 a with current. Other parts of the configuration are thesame as or similar to those described earlier, and thus descriptionthereof will be omitted.

FIG. 35 is a timing chart of reset driving. While a turn-on voltage isapplied to the gate signal line 17 a to turn on the transistor 11 b andreset the driver transistor 11 a, a turn-off voltage is applied to thegate signal line 17 b to keep the transistor 11 d off. This creates thestate shown in FIG. 32(a). A current Ib flows during this period.

Although in the timing chart shown in FIG. 35, the reset time is 2 Hs(when a turn-on voltage is applied to the gate signal line 17 a and thetransistor 11 b is turned on), this is not restrictive. The reset timemay be longer than 2 Hs. If a reset can be performed very quickly, thereset time may be less than 1 H.

The duration of the reset period can be changed easily using a DATA (ST)pulse period inputted in the gate driver circuit 12. For example, ifDATA inputted in an ST terminal is set high for a period of 2 Hs, thereset period outputted for each gate signal line 17 a is 2 Hs.Similarly, if DATA inputted in the ST terminal is set high for a periodof 5 Hs, the reset period outputted for each gate signal line 17 a is 5Hs.

After a reset period of 1 H, a turn-on voltage is applied to the gatesignal line 17 c(1) of the pixel row (1). As the transistor 11 c turnson, the programming current Iw applied to the source signal line 18 iswritten into the driver transistor 11 a via the transistor 11 c.

After current programming, a turn-off voltage is applied to the gatesignal line 17 c of the pixel row (1), the transistor 11 c is turnedoff, and the pixel disconnected from the source signal line. At the sametime, a turn-off voltage is also applied to the gate signal line 17 aand the driver transistor 11 a exits the reset mode (incidentally, theuse of the term “current-programming mode” is more appropriate than theterm “reset mode” to refer to this period). On the other hand, a turn-onvoltage is applied to the gate signal line 17 b, the transistor 11 d isturned on, and the current programmed into the driver transistor 11 aflows through the EL element 15. What has been said about the pixel row(1) similarly applies to the pixel row (2) and subsequent pixel rows.Also, their operation is obvious from FIG. 35. Thus, description of (2)and subsequent pixel rows will be omitted.

In FIG. 35, the reset period has been 1 H. FIG. 36 shows an example inwhich the reset period is 5 Hs. The duration of the reset period can bechanged easily using the DATA (ST) pulse period inputted in the gatedriver circuit 12. FIG. 36 shows an example in which DATA inputted inthe ST1 terminal of the gate driver circuit 12 a is set high for aperiod of 5 Hs and the reset period outputted for each gate signal line17 a is 5 Hs. The longer the reset period, the more completely the resetis performed, resulting in a proper black display. However, displaybrightness is decreased accordingly.

In FIG. 36, the reset period has been 5 Hs. Besides, the reset mode iscontinuous. However, the reset mode need not necessarily be continuous.For example, the signal outputted from each gate signal line 17 a may beturned on and off every 1 H. Such on/off operation can be achievedeasily by operating an enable circuit (not shown) formed in the outputstage of the shift register or controlling the DATA (ST) pulses inputtedin the gate driver circuit 12.

In the circuit configuration shown in FIG. 34, the gate driver circuit12 a requires at least two shift register circuits (one for the gatesignal line 17 a, the other for the gate signal line 17 b). Thispresents a problem of an increased circuit scale of the gate drivercircuit 12 a. FIG. 37 shows an example in which the gate driver circuit12 a has only one shift register. A timing chart of output signalsresulting from operation of the circuit in FIG. 37 is shown in FIG. 35.Note that the gate signal lines 17 coming out of the gate drivercircuits 12 a and 12 b are denoted by different symbols between FIGS. 35and 37.

As can be seen from the fact that an OR circuit 371 is included in FIG.37, the output of each gate signal line 17 a is ORed with the outputfrom the preceding stage to the shift register circuit 61 a. That is,the gate signal line 17 a outputs a turn-on voltage for a period of 2Hs. On the other hand, the gate signal line 17 c outputs the output ofthe shift register circuit 61 a as it is. Thus, a turn-on voltage isapplied for a period of 1 H.

For example, if the shift register circuit 61 a outputs a high-levelsignal second, a turn-on voltage is output to the gate signal lines 17 cof the pixel 16(1), which now is in a state of being programmed withcurrent (voltage). At the same time, a turn-on voltage is also output tothe gate signal lines 17 a of the pixel 16 (2), turning on thetransistor 11 b of the pixel 16(2) and resetting the driver transistor11 a of the pixel 16(2).

Similarly, if the shift register circuit 61 a outputs a high-levelsignal third, a turn-on voltage is output to the gate signal lines 17 cof the pixel 16(2), which now is in a state of being programmed withcurrent (voltage). At the same time, a turn-on voltage is also output tothe gate signal lines 17 a of the pixel 16(3, turning on the transistor11 b of the pixel 16(3) and resetting the driver transistor 11 a of thepixel 16(3). Thus, the gate signal lines 17 a outputs turn-on voltagesfor a period of 2 Hs, and the gate signal lines 17 c receive a turn-onvoltage for a period of 1 H.

In programming mode, since the transistors 11 b and 11 c turn onsimultaneously (FIG. 33(b)), if the transistor 11 c turns off before thetransistor 11 b during transition to non-programming mode (FIG. 33(c),the reset mode in FIG. 33(b) occurs. To prevent this situation, thetransistor 11 c must be turned off after the transistor 11 b. For that,a turn-on voltage needs to be applied to the gate signal line 17 aearlier than the gate signal line 17 c.

The above example concerns the pixel configuration in FIG. 32(basically, in FIG. 1). However, the present invention is not limited tothis. For example, it is also applicable to current-mirror pixelconfigurations such as the one shown in FIG. 38. Incidentally, in FIG.38, by turning on and off the transistor 11 e, N-fold pulse drivingillustrated in FIGS. 13, 15, etc. can be implemented. FIG. 39 is anexplanatory diagram illustrating an example employing the current-mirrorpixel configuration shown in FIG. 38. Reset driving in thecurrent-mirror pixel configuration will be described below withreference to FIG. 39.

As shown in FIG. 39(a), the transistors 11 c and 11 e are turned off andthe transistor 11 d is turned on. Then, the drain (D) terminal and gate(G) terminal of the current-programming transistor 11 b areshort-circuited and a current Ib flows between them as shown in thefigure. Generally, the transistor 11 b has been programmed with currentin the previous field (frame) and is capable of passing current (this isnatural because the gate potential is held in the capacitor 19 for aperiod of 1F and image is displayed. However, current does not flowduring a completely black display). In this state, as the transistor 11e is turned off and the transistor 11 d is turned on, the drive currentIb flows through the gate (G) terminal of the transistor 11 a (gate (G)terminal and the drain (D) terminal are short-circuited). Consequently,the gate (G) terminal and drain (D) terminal of the transistor 11 a havethe same potential, resetting the transistor 11 a (to a state in whichno current flows). Since the driver transistor 11 b shares a common gate(G) terminal with the current-programming transistor 11 a, the drivertransistor 11 b is also reset.

The reset mode (in which no current flows) of the transistors 11 a and11 b is equivalent to a state in which a offset voltage is held involtage offset canceling mode described with reference to FIG. 51 andthe like. That is, in the state in FIG. 39(a), the offset voltage isheld between the terminals of the capacitor 19 (the offset voltage is astarting voltage at which a current starts to flow: when a voltage equalto or larger than the starting voltage is applied, a current flowsthrough the transistor 11). The offset voltage varies with thecharacteristics of the transistors 11 a and 11 b. Thus, in FIG. 39(a), astate in which the transistors 11 a and 11 b do not pass current ismaintained in the capacitor 19 in each pixel (the transistors 11 a and11 b pass a black display current close to zero, i.e., they have beenreset to the starting voltage at which a current starts to flow).

In FIG. 39(a), as the reset period becomes longer, a larger Ib currenttends to flow, reducing the terminal voltage of the capacitor 19, as inthe case of FIG. 33(a). Thus, the operation time in FIG. 39(a) should befixed. It has been shown experimentally and analytically that preferablythe operation time in FIG. 39(a) is from 1 H to 10 Hs (ten horizontalscanning periods) both inclusive. More preferably, it should be from 1 Hto 5 Hs or from 20 μsec to 2 msec (both inclusive). This also applies tothe drive system in FIG. 33.

As in the case of FIG. 33(a), if the reset mode in FIG. 39(a) issynchronized with the current-programming mode in FIG. 39(b), there isno problem because the period from the reset mode in FIG. 39(a) to thecurrent-programming mode in FIG. 39(b) is fixed (constant). That is,preferably the period from the reset mode in FIG. 33(a) or FIG. 39(a) tothe current-programming mode in FIG. 33(b) or FIG. 39(b) should be from1 H to 10 Hs (ten horizontal scanning periods) both inclusive. Morepreferably, it should be from 1 H to 5 Hs or from 20 μsec to 2 msec(both inclusive). If this period is short, the driver transistors 11 arenot reset completely. If it is too long, the driver transistor 11 isturned off completely, which means that much time is required forcurrent programming. Also, the brightness of the screen 50 is decreased.

After the state in FIG. 39(a), a state shown in FIG. 39(b) occurs. FIG.39(b) shows a state in which the transistors 11 c and 11 d are turned onand the transistor 11 e is turned off. This is a state in which currentprogramming is being performed. Specifically, a programming current Iwis output (absorbed) from the source driver circuit 14 and passedthrough the current programming transistor 11 a. The potential of thegate (G) terminal of the driver transistor 11 a is set in the capacitor19 so that the programming current Iw will flow.

If the programming current Iw is 0 A (black display) the transistor 11 bis held in the state in FIG. 33(a) in which it does not pass current,and thus proper black display is achieved. Also, when performing currentprogramming for white display in FIG. 39(b), the current programming isstarted from offset voltage of completely black display even if thereare variations in the characteristics of driver transistors in pixels(the offset voltage is a starting voltage at which a current specifiedaccording to the characteristics of each driver transistor starts toflow). Thus, the time required to reach a target current value becomesuniform according to gradations. This eliminates gradation errors due tovariations in the characteristics of the transistor 11 a or 11 b, makingit possible to achieve proper image display.

After the current programming in FIG. 39(b), the transistors 11 c and 11d are turned off in sequence and the transistor 11 e is turned on todeliver the programming current Iw (=Ie) to the EL element 15 from thedriver transistor 11 b, and thereby illuminate the EL element 15. Whatis shown in FIG. 39(c) has already been described, and thus detaileddescription thereof will be omitted.

The drive system (reset driving) described with reference to FIGS. 33and 39 consists of a first operation of disconnecting the drivertransistor 11 a or 11 b from the EL element 15 (using the transistor 11e or 11 d so that no current flows) and shorting between the drain (D)terminal and gate (G) terminal of the driver transistor (or between thesource (S) terminal and gate (G) terminal, or generally speaking,between two terminals including the gate (G) terminal of the drivertransistor) and a second operation of programming the driver transistorwith current (voltage) after the first operation.

At least the second operation is performed after the first operation.Incidentally, the operation of disconnecting the driver transistor 11 aor 11 b from the EL element 15 in the first operation is not absolutelynecessary. The drain (D) terminal and gate (G) terminal of the drivertransistor are short-circuited in the first operation withoutdisconnecting the driver transistor 11 a or 11 b from the EL element 15,nothing more than some variations in reset mode may result. Whether toomit disconnection should be determined by considering thecharacteristics of the transistors in the constructed array.

The current-mirror pixel configuration in FIG. 39 provides a drivemethod which resets the current-programming transistor 11 a, andconsequently resets the driver transistor 11 b.

With the current-mirror pixel configuration in FIG. 39, it is not alwaysnecessary to disconnect the driver transistor 11 b from the EL element15 in reset mode. Thus, the following operations are performed: a firstoperation of shorting between the drain (D) terminal and gate (G)terminal of the current-programming transistor a (or between the source(S) terminal and gate (G) terminal, or generally speaking, between twoterminals including the gate (G) terminal of the current-programmingtransistor or between two terminals including the gate (G) terminal ofthe driver transistor) and a second operation of programming thecurrent-programming transistor with current (voltage) after the firstoperation. At least the second operation is performed after the firstoperation.

In image display mode (if instantaneous changes can be observed), thepixel row to be programmed with current is reset (black display mode)and is programmed with current after a predetermined H. The pixel row ofblack display moves from top to bottom of the screen and it should lookas if the image were rewritten at the location where the pixel rowpassed by.

Although the above example has been described mainly in relation topixel configuration for current programming, the reset driving accordingto the present invention can also be applied to pixel configuration forvoltage programming. FIG. 43 is an explanatory diagram illustrating apixel configuration (panel configuration) according to the presentinvention used to perform reset driving in a pixel configuration forvoltage programming.

In the configuration shown in FIG. 43, a transistor 11 e which resets adriver transistor 11 a has been formed. When a turn-on voltage isapplied to a gate signal line 17 e, the transistor 11 e turns on,causing a short circuit between the gate (G) terminal and drain (D)terminal of the driver transistor 11 a. Also a transistor 11 d whichcuts off a current path between the EL element 15 and driver transistor11 a has been formed. The reset driving according to the presentinvention in a pixel configuration for voltage programming will bedescribed below with reference to FIG. 44.

As illustrated in FIG. 44(a), the transistors 11 b and 11 d are turnedoff and the transistor 11 e is turned on. The drain (D) terminal andgate (G) terminal of the driver transistor 11 a are short-circuited anda current Ib flows as shown in the figure. Consequently, the gate (G)terminal and drain (D) terminal of the transistor 11 a have the samepotential, resetting the transistor 11 a (to a state in which no currentflows). Before resetting the transistor 11 a, the transistor 11 d isturned on, the transistor 11 e is turned off, and current is passedthrough the transistor 11 a in sync with an HD synchronization signal asdescribed with reference to FIG. 33 or 39. Then the operation shown inFIG. 44(a) is performed.

Incidentally, in the pixel configuration for voltage programming, as thereset period becomes longer, a larger Ib current tends to flow, reducingthe terminal voltage of the capacitor 19, as in the case of pixelconfiguration for current programming. Thus, the operation time in FIG.44(a) should be fixed. Preferably, the operation time should be from 0.2H to 5 Hs (five horizontal scanning periods) both inclusive. Morepreferably, it should be from 0.5 H to 4 Hs or from 2 μsec to 400 μsec(both inclusive).

Besides, it is preferable that the gate signal line 17 e should beshared with the gate signal line 17 a in a preceding stage. That is thegate signal line 17 e should be shorted to the gate signal line 17 a inthe pixel row in the preceding stage. This configuration is referred toas a preceding-stage gate control system. Incidentally, the stage-stagegate control system uses waveforms of gate signal lines of a pixel rowselected one or more Hs before the pixel row of interest. Thus, thissystem is not limited to the previous pixel row. For example, the drivertransistor 11 a of the pixel row of interest may be reset using thewaveforms of gate signal lines two pixel rows ahead.

The stage-stage gate control system will be described more concretely.Suppose, the pixel row of interest is the (N)-th pixel row whose gatesignal lines are 17 e(N) and 17 a(N) The preceding pixel row selected 1H before is assumed to be the (N−1)-th pixel row whose gate signal linesare 17 e(N−1) and 17 a (N−1). The pixel row selected 1 H after the pixelrow of interest is assumed to be the (N+1)-th pixel row whose gatesignal lines are 17 e(N+1) and 17 a(N+1).

In the (N−1)-th H-period, as a turn-on voltage is applied to the gatesignal line 17 a(N−1) of the (N−1)-th pixel row, a turn-on voltage isalso applied to the gate signal line 17 e(N) of the (N)-th pixel row.This is because the gate signal line 17 e (N) and the gate signal line17 a (N−1) of the pixel row in the preceding stage are shorted.Consequently, the pixel transistor 11 b(N−1) in the (N−1)-th pixel rowis turned on and the voltage applied to the source signal line 18 iswritten into the gate (G) terminal of the driver transistor 11 a (N−1).At the same time, the pixel transistor 11 e (N) in the (N)-th pixel rowis turned on, the gate (G) terminal and drain (D) terminal of the drivertransistor 11 a(N) are shorted, and the driver transistor 11 a(N) isreset.

In the (N)-th H-period which follows the (N−1)-th H-period, as a turn-onvoltage is applied to the gate signal line 17 a(N) of the (N)-th pixelrow, a turn-on voltage is also applied to the gate signal line 17 e(N+1)of the (N+1)-th pixel row. Consequently, the pixel transistor 11 b (N)in the (N)-th pixel row is turned on and the voltage applied to thesource signal line 18 is written into the gate (G) terminal of thedriver transistor 11 a (N). At the same time, the pixel transistor 11e(N+1) in the (N+1)-th pixel row is turned on, the gate (G) terminal anddrain (D) terminal of the driver transistor 11 a (N+1) are shorted, andthe driver transistor 11 a(N+1) is reset.

Similarly, in the (N+1)-th period which follows the (N)-th H-period, asa turn-on voltage is applied to the gate signal line 17 a (N+1) of the(N+1)-th pixel row, a turn-on voltage is also applied to the gate signalline 17 e(N+2) of the (N+2)-th pixel row. Consequently, the pixeltransistor 11 b(N+1) in the (N+1)-th pixel row is turned on and thevoltage applied to the source signal line 18 is written into the gate(G) terminal of the driver transistor 11 a(N+1). At the same time, thepixel transistor 11 e(N+2) in the (N+2)-th pixel row is turned on, thegate (G) terminal and drain (D) terminal of the driver transistor 11 a(N+2) are shorted, and the driver transistor 11 a(N+2) is reset.

According to the above-described stage-stage gate control system of thepresent invention, the driver transistor 11 a is reset for a period of 1H, and then voltage (current) programming is performed.

As in the case of FIG. 33(a), if the reset mode in FIG. 44(a) issynchronized with the voltage-programming mode in FIG. 44(b), there isno problem because the period from the reset mode in FIG. 44(a) to thecurrent-programming mode in FIG. 44(b) is fixed (constant). If thisperiod is short, the driver transistors 11 are not reset completely. Ifit is too long, the driver transistor 11 a is turned off completely,which means that much time is required for current programming. Also,the brightness of the screen 12 is decreased.

After the state in FIG. 44(a), a state shown in FIG. 44(b) occurs. FIG.44(b) shows a state in which the transistor 11 b is turned on and thetransistors 11 e and 11 d are turned off. This state in FIG. 44(b), is astate in which voltage programming is being performed. Specifically, aprogramming voltage is output from the source driver circuit 14 andwritten into the gate (G) terminal of the driver transistor 11 a (thepotential of the gate (G) terminal of the driver transistor 11 a is setin the capacitor 19). Incidentally, in the case of voltage programming,it is not always necessary to turn off the transistor 11 d duringvoltage programming. Besides, the transistor 11 e is not necessary ifthere is no need to combine with the N-fold driving shown in FIG. 13,15, or the like or perform intermittent N/K-fold pulse driving (thisdriving method provides two or more illuminated areas in a screen andcan be implemented easily by turning on and off the transistor 11 e).Since this has been described earlier, description thereof will beomitted.

When performing voltage programming for white display using theconfiguration shown in FIG. 43 or drive method shown in FIG. 44, thevoltage programming is started from offset voltage of completely blackdisplay even if there are variations in the characteristics of drivertransistors in pixels (the offset voltage is a starting voltage at whicha current specified according to the characteristics of each drivertransistor starts to flow). Thus, the time required to reach a targetcurrent value becomes uniform according to gradations. This eliminatesgradation errors due to variations in the characteristics of thetransistor 11 a, making it possible to achieve proper image display.

After the current programming in FIG. 44(b), the transistor 11 d isturned off and the transistor 11 d is turned on to deliver theprogramming current to the EL element 15 from the driver transistor 11a, and thereby illuminate the EL element 15, as shown in FIG. 44(c).

As described above, the reset driving according to the present inventionusing the voltage programming shown in FIG. 43 consists of a firstoperation of turning on the transistor 11 d, turning off the transistor11 e, and passing current through the transistor 11 a in sync with theHD synchronization signal; a second operation of disconnecting thetransistor 11 a from the EL element 15 and shorting between the drain(D) terminal and gate (G) terminal of the driver transistor 11 a (orbetween the source (S) terminal and gate (G) terminal, or generallyspeaking, between two terminals including the gate (G) terminal of thedriver transistor); and a third operation of programming the drivertransistor 11 a with voltage after the above operations.

In the above example, the transistor 11 d is turned on and off tocontrol the current delivered from the driver transistor 11 a (in thecase of configuration shown in FIG. 1) to the EL element 15. To turn onand off the transistor 11 d, the gate signal line 17 b needs to bescanned, for which the shift register circuit 61 (the gate drivercircuit 12) is required. However, shift register circuits 61 are largein scale and the use of a shift register circuit 61 for the gate signalline 17 b makes it impossible to reduce bezel width. A system describedwith reference to FIG. 40 solves this problem.

Incidentally, although the pixel configuration for current programmingillustrated in FIG. 1 and the like is mainly described herein by way ofexamples, the present invention is not limited to this and it goeswithout saying that the present invention can also be applied to otherconfiguration for current programming (current-mirror pixelconfiguration) described with reference to FIG. 38 and the like. Also,the technical concept of turning on and off elements as a block can alsobe applied to the pixel configuration for voltage programming in FIG. 41and the like.

FIG. 40 shows an example of a block driving system. For ease ofunderstanding, it is assumed that a gate driver circuit 12 is formeddirectly on an array board 71 or that a silicon chip, gate driver IC 12,is mounted on an array board 71. Source driver circuits 14 and sourcesignal lines 18 are omitted to avoid complicating the drawing.

In FIG. 40, gate signal lines 17 a are connected to the gate drivercircuit 12. On the other hand, gate signal lines 17 b are connected toillumination control lines 4 b 1. In FIG. 40, four gate signal lines 17b are connected to one illumination control line 401.

Incidentally, although four gate signal lines 17 b are grouped into ablock here, this is not restrictive and it goes without saying that morethan four gate signal lines 17 b may be grouped into a block. Generally,it is preferable to divide the screen 50 into five or more parts. Morepreferably, the screen 50 should be divided into ten or more parts. Evenmore preferably, the screen 50 should be divided into twenty or moreparts. A small number of divisions will make flickering conspicuous. Toolarge a number of divisions will increase the number of illuminationcontrol lines 401, making it difficult to lay out the illuminationcontrol lines 401.

Thus, in the case of a QCIF display panel, which has 220 verticalscanning lines, at least 220/5=44 or more lines should be grouped into ablock. More preferably, 220/10=11 or more lines should be grouped into ablock. However, if odd-numbered rows and even-numbered rows are groupedinto two different blocks, there is not much flickering even at a lowframe rate, and thus the two blocks are sufficient.

In the example shown in FIG. 40, the current flowing through the ELelements 15 are turned on and off on a block-by-block basis by theapplication of either a turn-on voltage (Vgl) or turn-off voltage (Vgh)to illumination control lines 401 a, 401 b, 401 c, 401 d, . . . , 401 nin sequence.

Incidentally, in the example in FIG. 40, the gate signal lines 17 b donot intersect the illumination control lines 401. Thus, there can be nodefect in which a gate signal line 17 b would become short-circuitedwith an illumination control line 401. Also, since there is nocapacitive coupling between gate signal lines 17 b and illuminationcontrol lines 401, addition of capacitance is very small when the gatesignal lines 17 b are viewed from the illumination control lines 401.This makes it easy to drive the illumination control lines 401.

The gate driver circuit 12 is connected with the gate signal lines 17 a.When a turn-on voltage is applied to gate signal lines 17 a, theappropriate pixel rows are selected and the transistors 11 b and 11 c inthe selected pixel rows are turned on. Then, currents (voltage) appliedto the source signal lines 18 are programmed into the capacitors 19 inthe pixels. On the other hand, the gate signal lines 17 b are connectedwith the gate (G) terminals of the transistors 11 d in the pixels. Thus,when a turn-on voltage (Vgl) is applied to the illumination controllines 401, current paths are formed between the driver transistors 11 aand EL elements 15. When a turn-off voltage (Vgh) is applied, the anodeterminals of the EL elements 15 are opened.

Preferably, control timing of turn-on/turn-off voltages applied to theillumination control lines 401 and a pixel row selection voltage (Vgl)outputted to the gate signal lines 17 a by the gate driver circuit 12are synchronized with one horizontal scanning clock (1 H). However, thisis not restrictive.

The signals applied to the illumination control lines 401 simply turn onand off the current delivered to the EL elements 15. They do not need tobe synchronized with image data outputted from the source drivercircuits 14. This is because the signals applied to the illuminationcontrol lines 401 are intended to control the current programmed intothe capacitors 19 in the pixels 16. Thus, they do not always need to besynchronized with the pixel row selection signal. Even when they aresynchronized, the clock is not limited to a 1-H signal and may be a1/2-H or 1/4-H signal.

Even in the case of the current-mirror pixel configuration shown in FIG.38, the transistors 11 e can be turned on and off if the gate signallines 17 b are connected to the illumination control lines 401. Thus,block driving can be implemented.

Incidentally, in FIG. 32, by connecting the gate signal lines 17 a tothe illumination control lines 401 and performing resets, it is possibleto implement block driving. In other words, the block driving accordingto the present invention is a drive method which puts a plurality ofpixel rows in non-illumination (black display) mode simultaneously usingone control line.

In the above example, one selection pixel row is placed (formed) perpixel row. The present invention is not limited to this and a selectiongate signal line may be placed (formed) for two or more pixel rows.

FIG. 41 shows such an example. Incidentally, for ease of explanation,the pixel configuration in FIG. 1 is employed mainly. In FIG. 41, thegate signal line 17 a for pixel row selection selects three pixels (16R,16G, and 16B) simultaneously. Reference character R is intended toindicate something related to a red pixel, reference character Gindicates something related to a green pixel, and reference character Bindicates something related to a blue pixel.

Thus, when the gate signal line 17 a is selected, the pixels 16R, 16G,and 16B are selected and get ready to write data. The pixel 16R writesdata into a capacitor 19R via a source signal line 18R, the pixel 16Gwrites data into a capacitor 19G via a source signal line 18G, and thepixel 16B writes data into a capacitor 19B via a source signal line 18B.

The transistor 11 d of the pixel 16R is connected to a gate signal line17 bR, the transistor 11 d of the pixel 16G is connected to a gatesignal line 17 bG, and the transistor 11 d of the pixel 16B is connectedto a gate signal line 17 bB. Thus, an EL element 15R of the pixel 16R,EL element 15G of the pixel 16G, and EL element 15B of the pixel 16B canbe turned on and off separately. Illumination times and illuminationperiods of the EL element 15R, EL element 15G, and EL element 15B can becontrolled separately by controlling the gate signal line 17 bR, gatesignal line 17 bG, and gate signal line 17 bB.

To implement this operation, in the configuration in FIG. 6, it isappropriate to form (place) four shift register circuits: a shiftregister circuit 61 which scans the gate signal line 17 a, shiftregister circuit 61 which scans the gate signal line 17 bR, shiftregister circuit 61 which scans the gate signal line 17 bG, and shiftregister circuit 61 which scans the gate signal line 17 bB.

Incidentally, although it has been stated that a current N times largerthan a predetermined current is passed through the source signal line 18and that a current N times larger than a predetermined current is passedthrough the EL element 15 for a period of 1/N, this cannot beimplemented in practice. Actually, signal pulses applied to the gatesignal line 17 penetrate into the capacitor 19, making it impossible toset a desired voltage value (current value) on the capacitor 19.Generally, a voltage value (current value) lower than a desired voltagevalue (current value) is set on the capacitor 19. For example, even if10 times larger current value is meant to be set, only approximately 5times larger current value is set on the capacitor 19. For example, evenif N=10 is specified, N=5 times larger current actually flows throughthe EL element 15. Thus, this method sets an N times larger currentvalue to pass a current proportional or corresponding to the N-foldvalue through the EL element 15. Alternatively, this drive methodapplies a current larger than a desired value to the EL element 15 in apulsed manner.

This method performs current (voltage) programming so as to obtaindesired emission brightness of the EL element by passing a currentlarger than a desired value intermittently through the driver transistor11 a (in the case of FIG. 1) (i.e., a current which will give brightnesshigher than the desired brightness if passed through the EL element 15continuously).

Preferably, N-channel transistors are used as the switching transistors11 b and 11 c, etc. in FIG. 1 and the like. This will reduce penetrationvoltage reaching the capacitor 19. Also, since off-leakage of thecapacitor 19 is reduced, this method can be applied to a 10-Hz or lowerframe rate.

Depending on pixel configuration, if the penetration voltage tends toincrease the current flowing through the EL element 15, white peakvoltage will increase, increasing perceived contrast in image display.This provides for a good image display.

Conversely, it is also useful to use P-channel transistors as theswitching transistors 11 b and 11 c in FIG. 1 to cause penetration, andthereby obtain a proper black display. When the P-channel transistor 11b turns off, the voltage goes high (Vgh), shifting the terminal voltageof the capacitor 19 slightly to the Vdd side. Consequently, the voltageat the gate (G) terminal of the transistor 11 a rises, resulting in moreintense black display. Also, the current used for first gradationdisplay can be increased (a certain base current can be delivered upuntil gradation 1), and thus shortages of write current can be easedduring current programming.

Another drive method according to the present invention will bedescribed below with reference to drawings. FIG. 125 is an explanatorydiagram illustrating a display panel which performs sequential drivingaccording to the present invention. A source driver circuit 14 outputsR, G, and B data to connection terminals 618 by switching among them.Thus, the source driver circuit 14 only needs 1/3 as many outputterminals as in FIG. 48.

Signals outputted from the source driver circuit 14 to the connectionterminals 681 are allocated to 18R, 18G, and 18B by an output switchingcircuit 1251. The output switching circuit 1251 is formed directly on anarray board 71 by polysilicon technology or amorphous silicontechnology. Alternatively, it may be formed with silicon chips andmounted on the array board 71 by COG, TAB, or COF technology. Also, theoutput switching circuit 1251 may be incorporated into the source drivercircuit 14 as a sub-circuit of the source driver circuit 14.

If a changeover switch 1252 is connected to an R terminal, the outputsignal from the source driver circuit 14 is applied to the source signalline 18R. If the changeover switch 1252 is connected to a G terminal,the output signal from the source driver circuit 14 is applied to thesource signal line 18G. If the changeover switch 1252 is connected to aB terminal, the output signal from the source driver circuit 14 isapplied to the source signal line 18B.

Incidentally, in the configuration in FIG. 126, when the changeoverswitch 1252 is connected to the R terminal, the G terminal and Bterminal of the changeover switch are open. Thus, the current enteringthe source signal lines 18G and 18B is 0 A. Consequently, the pixels 16connected to the source signal lines 18G and 18B provide a blackdisplay.

When the changeover switch 1252 is connected to the G terminal, the Rterminal and B terminal of the change over switch are open. Thus, thecurrent entering the source signal lines 18R and 18B is 0 A.Consequently, the pixels 16 connected to the source signal lines 18R and18B provide a black display.

In the configuration in FIG. 126, when the changeover switch 1252 isconnected to the B terminal, the R terminal and G terminal of thechangeover switch are open. Thus, the current entering the source signallines 18R and 18G is 0 A. Consequently, the pixels 16 connected to thesource signal lines 18R and 18G provide a black display.

Basically, if one frame consists of three fields, R image data iswritten in sequence into the pixels 16 in the screen 50 in the firstfield. In the second field, G image data is written in sequence into thepixels 16 in the screen 50. In the third field, B image data is writtenin sequence into the pixels 16 in the screen 50.

Thus, R data→G data→B data→R data→G data→B data→R data→ . . . arerewritten in sequence in the appropriate fields to implement sequentialdriving. Description of how N-fold pulse driving is performed by turningon and off the switching transistor 11 d as shown in FIG. 1 has beengiven with reference to FIGS. 5, 13, 16, etc. Needless to say, such adrive method can be combined with sequential driving. Of course, it goeswithout saying that other drive methods according to the presentinvention can be combined with sequential driving.

In the above example, it has been stated that when image data is writteninto the R pixel 16, black data is written into the G pixel and B pixel,that when image data is written into the G pixel 16, black data iswritten into the R pixel and B pixel, and that when image data iswritten into the B pixel 16, black data is written into the R pixel andG pixel. The present invention is not limited to this.

For example, when image data is written into the R pixel 16, the G pixeland B pixel may retain the image data rewritten in the previous field.This can make the screen 50 brighter. When image data is written intothe G pixel 16, the R pixel and B pixel may retain the image datarewritten in the previous field. When image data is written into the Bpixel 16, the G pixel and R pixel may retain the image data rewritten inthe previous field.

In order to retain image data in pixels other than the color pixel beingrewritten, the gate signal line 17 a can be controlled separately forthe R, G, and B pixels. For example, as illustrated in FIG. 125, a gatesignal line 17 aR can be designated as a signal line which turns on andoff the transistors 11 b and 11 c of the R pixel, a gate signal line 17aG can be designated as a signal line which turns on and off thetransistors 11 b and 11 c of the G pixel, and a gate signal line 17 aBcan be designated as a signal line which turns on and off thetransistors 11 b and 11 c of the B pixel. On the other hand, the gatesignal line 17 b can be designated as a signal line which commonly turnson and off the transistors 11 d of the R, G, and B pixels.

With the above configuration, when the source driver circuit 14 outputsR image data and the changeover switch 1252 is set to an R contact, aturn-on voltage can be applied to the gate signal line 17 aR and aturn-off voltage can be applied to the gate signal lines aG and aB.Thus, the R image data can be written into the R pixel 16 and the Gpixel 16 and R pixel 16 can retain the image data of the previous field.

When the source driver circuit 14 outputs G image data in the secondfield and the changeover switch 1252 is set to a G contact, a turn-onvoltage can be applied to the gate signal line 17 aG and a turn-offvoltage can be applied to the gate signal lines aR and aB. Thus, the Gimage data can be written into the G pixel 16 and the R pixel 16 and Bpixel 16 can retain the image data of the previous field.

When the source driver circuit 14 outputs B image data in the thirdfield and the changeover switch 1252 is set to a B contact, a turn-onvoltage can be applied to the gate signal line 17 aB and a turn-offvoltage can be applied to the gate signal line aR and aG. Thus, the Bimage data can be written into the B pixel 16 and the R pixel 16 and Gpixel 16 can retain the image data of the previous field.

In the example shown in FIG. 125, the gate signal lines 17 a are placed(formed) in such a way as to turns on and off the transistors 11 b ofthe R, G, and B pixels 16 separately. However, the present invention isnot limited to this. For example, a gate signal line 17 a common to theR, G, and B pixels 16 may be formed of placed as illustrated in FIG.126.

In relation to the configuration in FIG. 125 and the like, it has beenstated that when the R source signal line is selected by the changeoverswitch 1252, the G and B source signal lines are open. However, the openstate is an electrically floating state and is not desirable.

FIG. 126 shows a configuration in which measures are taken to eliminatesuch floating state. A terminal a of a changeover switch 1252 of anoutput switching circuit 1251 is connected to a Vaa voltage (voltage forblack display) A terminal b is connected to an output terminal of thesource driver circuit 14. The changeover switch 1252 is installed foreach of the R, G, and B pixels.

In the state shown in FIG. 126, a changeover switch 1252R is connectedto a Vaa terminal. Thus, the Vaa voltage (voltage for black display) isapplied to the source signal line 18R. A changeover switch 1252G isconnected to a Vaa terminal. Thus, the Vaa voltage (voltage for blackdisplay) is applied to the source signal line 18G. A changeover switch1252B is connected to the output terminal of the source driver circuit14. Thus, a B image signal is applied to the source signal line 18B.

In the above state, the B pixel is being rewritten and a black displayvoltage is applied to the R pixel and G pixel. As the changeoverswitches 1252 are controlled in the above manner, an image composed ofthe pixels 16 are rewritten. Incidentally, control of the gate signallines 17 b is the same as in the examples described above, and thusdetailed description thereof will be omitted.

In the above example, the R pixel 16 is rewritten in the first field,the G pixel 16 is rewritten in the second field, and the B pixel 16 isrewritten in the third field. That is, the color of the pixel rewrittenchanges every field. The present invention is not limited to this. Thecolor of the pixel rewritten may be changed every horizontal scanningperiod (1 H). For example, a possible drive method involves rewritingthe R pixel in the first H, the G pixel in the second H, the B pixel inthe third H, the R pixel in the fourth H, and so on. Of course, thecolor of the pixel rewritten may be changed every two horizontalscanning periods or every 1/3 field.

FIG. 127 shows an example, in which the color of the pixel rewrittenchanges every 1 H. Incidentally, in FIGS. 127 to 129, the obliquehatching indicates that the pixels 16 either retain image data from theprevious field instead of being rewritten or are displayed in black. Ofcourse, the black display of the pixels and retention of image data fromthe previous field may be repeated alternately.

Needless to say, in the drive system in FIGS. 125 to 129, it is alsopossible to use the N-fold pulse driving in FIG. 13 or simultaneousM-row driving. FIGS. 125 to 129 show writing of pixels 16. Althoughillumination control of the EL elements 15 is not described, it goeswithout saying that this example can be used in combination withexamples described earlier or later. Of course, this drive method can becombined with the configuration which involves formation of the dummypixel rows 271 described with reference to FIG. 27 and a drive methodwhich uses the dummy pixel rows.

One frame need not necessarily consist of three fields and may consistof two fields or four or more fields. In one example illustrated herein,one frame consists of two fields and the R and G pixels out of the threeprimary RGB colors are rewritten in the first field and the B pixel isrewritten in the second field. In another example illustrated herein,one frame consists of four fields and the R pixel out of the threeprimary RGB colors is rewritten in the first field, the G pixel isrewritten in the second field, and the B pixel is rewritten in the thirdand fourth field. In these sequences, white balance can be achieved moreefficiently if the luminous efficiencies of the R, G, and B EL elements15 are taken into consideration.

In the above example, the R pixel 16 is rewritten in the first field,the G pixel 16 is rewritten in the second field, and the B pixel 16 isrewritten in the third field. That is, the color of the pixel rewrittenchanges every field.

According to the example shown in FIG. 127, in the first field, an Rpixel is rewritten in the first H, a G pixel is rewritten in the secondH, a B pixel is rewritten in the third H, an R pixel is rewritten in thefourth H, and so on. Of course, the color of the pixel rewritten may bechanged every two or more horizontal scanning periods or every 1/3field.

According to the example shown in FIG. 127, in the first field, an Rpixel is rewritten in the first H, a G pixel is rewritten in the secondH, a B pixel is rewritten in the third H, and an R pixel is rewritten inthe fourth H. In the second field, a G pixel is rewritten in the firstH, a B pixel is rewritten in the second H, an R pixel is rewritten inthe third H, and a G pixel is rewritten in the fourth H. In the thirdfield, a B pixel is rewritten in the first H, an R pixel is rewritten inthe second H, a G pixel is rewritten in the third H, and a B pixel isrewritten in the fourth H.

Thus, by rewriting the R, G, and B pixels in each field arbitrarily orwith some regularity, it is possible to prevent separation among the R,G, and B colors. Also, flickering is reduced.

In FIG. 128, a plurality of pixel 16 colors are rewritten every 1 H. InFIG. 127, in the first field, the pixel 16 rewritten in the first H isan R pixel, the pixel 16 rewritten in the second H is a G pixel, thepixel 16 rewritten in the third H is a B pixel, the pixel 16 rewrittenin the fourth H is an R pixel.

In FIG. 128, positions of the different-colored pixels rewritten arechanged every 1 H. By assigning R, G, and B pixels to different fields(needless to say, this may be done with some regularity) and rewritingthem in sequence, it is possible to prevent separation among the R, G,and B colors as well as to reduce flickering.

Incidentally, even in the example in FIG. 128, the R, G, and B pixelsshould have the same illumination time or luminous intensity in eachpicture element, which is a set of R, G, and B pixels. Needless to say,this is also done in the examples in FIGS. 126, 127, and the like toavoid color irregularities.

As shown in FIG. 128, in order to rewrite pixels of different colors ineach H (three colors—R, G, and B—are rewritten in the first H in thefirst field in FIG. 128), in FIG. 125, the source driver circuit 14 canbe configured to output image signals of arbitrary colors (or colorsdetermined with some regularity) to the terminals and the changeoverswitches 1252 can be configured to connect to the R, G, and B contactsarbitrarily (or with some regularity) The panel in an example in FIG.129 has W (white) pixels 16W in addition to the three primary colorsRGB. By forming or placing pixels 16W, it is possible to achieve peakbrightness of colors properly as well as to achieve a highbrightness-display. FIG. 129(a) shows an example in which R, G, B, and Wpixels 16 are formed in each pixel row. FIG. 129(b) shows an example inwhich R, G, B, and W pixels are placed in turns in different pixel rows.

Needless to say, the drive method in FIG. 129 can incorporate the drivemethods in FIGS. 127, 128, etc. Also, it goes without saying that N-foldpulse driving, simultaneous M-row driving, etc. can be incorporated.These matters can easily be implemented by those skilled in the artbased on this specification, and thus description thereof will beomitted.

Incidentally, for ease of explanation, it is assumed that the displaypanel according to the present invention has the three primary colorsRGB, but this is not restrictive. The display panel may have cyan,yellow, and magenta in addition to R, G, and B, or it may have any oneof R, G, and B or any two of R, G, and B.

Also, although it has been stated that the sequential driving systemhandles R, G, and Bin each field, it goes without saying that thepresent invention is not limited to this. Besides, the examples in FIGS.125 to 129 illustrate how image data is written into pixels 16. They donot illustrate (although, of course, they are related to) a method ofdisplaying images by operating the transistors 11 d and passing currentthrough the EL elements 15 unlike in FIG. 1. In the configuration shownin FIG. 1, current is passed through the EL elements 15 by controllingthe transistors 11 d.

Also, the drive methods in FIGS. 127, 128, etc. can display RGB imagesin sequence by controlling the transistors 11 d (in the case of FIG. 1).For example, in FIG. 130(a) an R display area 53R, G display area 53G,and B display area 53B are scanned from top to bottom (or from bottom totop) of the screen during one frame (one field) period. The remainingarea becomes a non-display area 52. That is, intermittent driving isperformed.

FIG. 130(b) shows an example in which a plurality of RGB display areas53 are generated during one field (one frame) period. This drive methodis analogous to the one shown in FIG. 16. Thus, it will require noexplanation. In FIG. 130(b), by dividing the display area 53, it ispossible to eliminate flickering even at a lower frame rate.

FIG. 131(a) shows a case in which R, G, and B display areas 53 havedifferent sizes (needless to say, the size of a display area 53 isproportional to its illumination period). In FIG. 131(a), the R displayarea 53R and G display area 53G have the same size. The B display area53B has a larger size than the G display area 53G. In an organic ELdisplay panel, B often has a low light emission efficiency. By makingthe B display area 53B larger than the display areas 53 of other colorsas shown in FIG. 131(a), it is possible to achieve a white balanceefficiently.

FIG. 131(b) shows an example in which there are a plurality of B displayperiods 53B (53B1 and 53B2) during one field (one frame) period. WhereasFIG. 131(a) shows a method of varying the size of one B display area 53Bto allow the white balance to be adjusted properly, FIG. 131(b) shows amethod of displaying multiple B display areas 53B having the samesurface area to achieve a proper white balance.

The drive system according to the present invention is not limited toeither FIG. 131(a) or FIG. 131(b). It is intended to generate R, G, andB display areas 53 and create an intermittent display, and therebycorrect blurred moving pictures and insufficient writing into the pixels16. With the drive method in FIG. 16, independent display areas 53 forR, G, and B are not generated. R, G, and B are displayed simultaneously(it should be stated that a W display area 53 is presented).Incidentally, it goes without saying that FIG. 131(a) and FIG. 131(b)may be combined. For example, it is possible to combine the drive methodof using display areas 53 of different sizes for R, G, and B in FIG.131(a) with the drive method of generating multiple display areas 53 forR, G, or B in FIG. 131(b).

Incidentally, the drive method in FIGS. 130 and 131 is not limited tothe drive methods in FIGS. 125 to 129 according to the presentinvention. Needless to say, with a configuration in which the currentsflowing through the EL elements 15 (EL elements 15R, EL elements 15G,and EL elements 15B) are controlled separately for R, G, and B as shownin FIG. 41, the drive method in FIGS. 130 and 131 can be implementedeasily. By applying turn-on/turn-off voltages to the gate signal line 17bR, it is possible to turn on and off the R pixel 16R. By applyingturn-on/turn-off voltages to the gate signal line 17 bG, it is possibleto turn on and off the G pixel 16G. By applying turn-on/turn-offvoltages to the gate signal line 17 bB, it is possible to turn on andoff the B pixel 16B.

The above driving can be implemented by forming or placing a gate drivercircuit 12 bR which controls the gate signal line 17 bR, a gate drivercircuit 12 bG which controls the gate signal line 17 bG, and a gatedriver circuit 12 bB which controls the gate signal line 17 bB, asillustrated in FIG. 132. By driving the gate driver circuits 12 bR, 12bG, and 12 bB in FIG. 132 by the method described in FIG. 6 or the like,the drive method in FIGS. 130 and 131 can be implemented. Of course, itgoes without saying that the drive methods in FIG. 16 and the like canbe implemented using the configuration of the display panel in FIG. 132.

Also, with the configuration shown in FIGS. 125 to 128, the drive methodin FIGS. 130 and 131 can be implemented using a gate signal line 17 bcommon to the R, G, and B pixels without using a gate signal line 17 bRwhich controls the EL elements 15R, a gate signal line 17 bG whichcontrols the EL elements 15G, and a gate signal line 17 bB whichcontrols the EL elements 15B as long as black image data can be writteninto pixels 16 other than the pixels 16 whose image data is rewritten.

It has been stated with reference to FIGS. 15, 18, 21, etc. that thegate signal line 17 b (EL-side selection signal line) applies a turn-onvoltage (Vgl) and turn-off voltage (Vgh) every horizontal scanningperiod (1 H). However, in the case of a constant current, light emissionquantity of the EL elements 15 is proportional to the duration of thecurrent. Thus the duration is not limited to 1 H.

To introduce a concept of output enable (OEV), the following provisionsare made. By performing OEV control, turn-on and turn-off voltages (Vglvoltage and Vgh voltage) can be applied to the pixels 16 from the gatesignal line 17 a and 17 b within one horizontal scanning period (1 H).

For ease of explanation, it is assumed that in the display panelaccording to the present invention, the pixel rows to be programmed withcurrent are selected by the gate signal line 17 a (in the case of FIG.1). The output from the gate driver circuit 12 a which controls the gatesignal line 17 a is referred to as a WR-side selection signal line.Also, it is assumed that EL elements 15 are selected by the gate signalline 17 b (in the case of FIG. 1). The output from the gate drivercircuit 12 b which controls the gate signal line 17 b is referred to asan EL-side selection signal line.

The gate driver circuits 12 are fed a start pulse, which is shifted asholding data in sequence within a shift register. Based on the holdingdata in the shift register of the gate driver circuit 12 a, it isdetermined whether to output a turn-on voltage (Vgl) or turn-off voltage(Vgh) to the WR-side selection signal line. An OEV1 circuit (not shown)which turns off output forcibly is formed or placed in an output stageof the gate driver circuit 12 a. When the OEV1 circuit is low, a WR-sideselection signal which is an output of the gate driver circuit 12 a isoutput as it is to the gate signal line 17 a. The above relationship isillustrated logically in FIG. 224(a) (OR circuit). Incidentally, theturn-on voltage is set at logic level L (0) and the turn-off voltage isset at logic voltage H (1).

That is, when the gate driver circuit 12 a outputs a turn-off voltage,the turn-off voltage is applied to the gate signal line 17 a. When thegate driver circuit 12 a outputs a turn-on voltage (logic low), it isORed with the output of the OEV1 circuit by the OR circuit and theresult is output to the gate signal line 17 a. That is, when the OEV1circuit is high, the turn-off voltage (Vgh) is output to the gate driversignal line 17 a (see an exemplary timing chart in FIG. 176).

Based on holding data in a shift register of the gate driver circuit 12b, it is determined whether to output a turn-on voltage (Vgl) orturn-off voltage (Vgh) to the gate signal line 17 b (EL-side selectionsignal line). An OEV2 circuit (not shown) which turns off outputforcibly is formed or placed in an output stage of the gate drivercircuit 12 b. When the OEV2 circuit is low, an output of the gate drivercircuit 12 b is output as it is to the gate signal line 17 b. The aboverelationship is illustrated logically in FIG. 176(a). Incidentally, theturn-on voltage is set at logic level L (0) and the turn-off voltage isset at logic voltage H (1).

That is, when the gate driver circuit 12 b outputs a turn-off voltage(an EL-side selection signal is a turn-off voltage), the turn-offvoltage is applied to the gate signal line 17 b. When the gate drivercircuit 12 b outputs a turn-on voltage (logic low), it is ORed with theoutput of the OEV2 circuit by the OR circuit and the result is output tothe gate signal line 17 b. That is, when an input signal is high, theOEV2 circuit outputs the turn-off voltage (Vgh) to the gate driversignal line 17 b. Thus, even if the EL-side selection signal from theOEV2 circuit is a turn-on voltage, the turn-off voltage (Vgh) is outputforcibly to the gate signal line 17 b. Incidentally, if an input to theOEV2 circuit is low, the EL-side selection signal is output directly tothe gate signal line 17 b (see the exemplary timing chart in FIG. 176).

Incidentally, screen brightness is adjusted under the control of OEV2.There are permissible limits to changes in screen brightness. FIG. 175illustrates relationship between permissible changes (%) and screenbrightness (nt) As can be seen from FIG. 175, relatively dark imageshave small permissible changes. Thus, in performing brightnessadjustments of the screen 50 under the control of OEV2 or through dutycycle control, the brightness of the screen 50 should be taken intoconsideration. Permissible changes should be shorter when the screen isdark than when it is bright.

FIG. 140 shows 1/4-duty ratio driving. A turn-on voltage is applied tothe gate signal line 17 b (EL-side selection signal line) every 4 Hs andthe locations to which the turn-on voltage is applied are scanned insync with a horizontal synchronization signal (HD). Thus, the unitlength of a conduction period is 1 H.

However, the present invention is not limited to this. The duration ofthe conduction period may be less than 1 H (1/2 H in FIG. 143) as shownin FIG. 143 or it may be equal to or less than 1 H. In short, the unitlength of the conduction period is not limited to 1 H and a unit lengthother than 1 H can be generated easily using the OEV2 circuit formed orplaced in the output stage of the gate driver circuit 12 b (circuitwhich controls the gate signal line 17 b). The OEV2 circuit is similarto the OEV1 circuit described earlier, and thus description thereof willbe omitted.

In FIG. 141, the conduction period of the gate signal line 17 b (EL-sideselection signal line) does not have a unit length of 1 H. A turn-onvoltage little shorter than 1 H is applied to the gate signal lines 17 b(EL-side selection signal lines) in odd-numbered pixel rows. A turn-onvoltage is applied to the gate signal lines 17 b (EL-side selectionsignal lines) in even-numbered pixel rows for a very short period. Theduration T1 of the turn-on voltage applied to the gate signal lines 17 b(EL-side selection signal lines) in odd-numbered pixel rows plus theduration T2 of the turn-on voltage applied to the gate signal lines 17 b(EL-side selection signal lines) in even-numbered pixel rows is designedto be 1 H. FIG. 141 shows a state of the first field.

In the second field which follows the first field, a turn-on voltagelittle shorter than 1 H is applied to the gate signal lines 17 b(EL-side selection signal lines) in even-numbered pixel rows. A turn-onvoltage is applied to the gate signal lines 17 b (EL-side selectionsignal lines) in odd-numbered pixel rows for a very short period. Theduration T1 of the turn-on voltage applied to the gate signal lines 17 b(EL-side selection signal lines) in even-numbered pixel rows plus theduration T2 of the turn-on voltage applied to the gate signal lines 17 b(EL-side selection signal lines) in odd-numbered pixel rows is designedto be 1 H.

The sum duration of turn-on voltage applications to gate signal lines 17b in a plurality of pixel rows may be designed to be constant.Alternatively, the illumination time of each EL element 15 in each pixelrow in each field may be designed to be constant.

FIG. 142 shows a case in which the conduction period of the gate signalline 17 b (EL-side selection signal line) is 1.5 Hs. The rise and fallof the gate signal line 17 b at point A are designed to overlap. Thegate signal line 17 b (EL-side selection signal line) and source signalline 18 are coupled. Thus, any change in a waveform of the gate signalline 17 b (EL-side selection signal line) penetrates to the sourcesignal line 18. Consequently, any potential fluctuation in the sourcesignal line 18 lowers accuracy of current (voltage) programming, causingirregularities in the characteristics of the driver transistors 11 a toappear in the display.

Referring to FIG. 142, at point A, the voltage applied to the gatesignal line 17B (EL-side selection signal line) (1) changes from turn-onvoltage (Vgl) to turn-off voltage (Vgh). The voltage applied to the gatesignal line 17B (EL-side selection signal line) (2) changes fromturn-off voltage (Vgh) to turn-on voltage (Vgl). Thus, at point A, thesignal waveform of the gate signal line 17B (EL-side selection signalline) (1) and the signal waveform of the gate signal line 17B (EL-sideselection signal line) (2) cancel out each other. Consequently, even ifthe gate signal line 17B (EL-side selection signal line) and sourcesignal line 18 are coupled, changes in the waveform of the gate signalline 17 b (EL-side selection signal line) do not penetrate to the sourcesignal line 18. This improves the accuracy of current (voltage)programming, resulting in a uniform image display.

Incidentally, in the example in FIG. 142, the conduction period is 1.5Hs. However, the present invention is not limited to this. Needless tosay, the duration of application of the turn-on voltage may be 1 H orless as illustrated in FIG. 144.

By adjusting the duration of application of the turn-on voltage to thegate signal line 17B (EL-side selection signal line), it is possible toadjust the brightness of the display screen 50 linearly. This can bedone easily through control of the OEV2 circuit. Referring to FIG. 145,for example, display brightness in FIG. 145(b) is lower than in FIG.145(a). Also, display brightness in FIG. 145(c) is lower than in FIG.145(b).

FIG. 109 illustrates relationship between OEV2 and the signal waveformof the gate signal line 17 b. In FIG. 109, the period during which OEV2is low is the shortest in FIG. 109(a). Consequently, the turn-on voltageis applied to the gate signal line 17 b for a short period of time,meaning that current flows through the EL element 15 for a short periodof time. This results in a small duty ratio. In FIG. 109(b), the periodduring which OEV2 is low is longer. In FIG. 109(c) the period duringwhich OEV2 is low is longer than in FIG. 109(b). Thus, the duty ratio inFIG. 109(c) is larger than in FIG. 109(b).

Incidentally, in the examples in FIGS. 109(a), 109(b) and 109(c), dutycycle control is performed in a period shorter than 1 H. However, thepresent invention is not limited to this. The unit duration of dutycycle control may be 1 H as shown in FIG. 109(d). FIG. 109(d) shows anexample in which the duty ratio is 1/2.

The period during which OEV2 is low is the shortest in FIG. 109(a).Consequently, the turn-on voltage is applied to the gate signal line 17b for a short period of time, meaning that current flows through the ELelement 15 for a short period of time. This results in a small dutyratio.

The period during which OEV2 is low is the shortest in FIG. 109(a).Consequently, the turn-on voltage is applied to the gate signal line 17b for a short period of time, meaning that current flows through the ELelement 15 for a short period of time. This results in a small dutyratio.

As shown in FIG. 146, multiple sets of turn-on voltage and turn-offvoltage may be applied in a period of 1 H. FIG. 146(a) shows an examplein which six sets are applied. FIG. 146(b) shows an example in whichthree sets are applied. FIG. 146(c) shows an example in which one set isapplied. In FIG. 146, display brightness is lower in FIG. 146(b) than inFIG. 146(a). It is lower in FIG. 146(c) than in FIG. 146(b). Thus, bycontrolling the number of conduction periods, display brightness can beadjusted (controlled) easily.

The current-driven source driver IC (circuit) 14 according to thepresent invention will be described below. The source driver ICaccording to the present invention is used to implement the drivemethods and drive circuits according to the present invention describedearlier. It is used in combination with drive methods, drive circuits,and display apparatus according to the present invention. Incidentally,although the source driver circuit will be described as an IC chip, thisis not restrictive and the source driver circuit may be built on thearray board 71 of the display panel using low-temperature polysilicontechnology, amorphous silicon technology, or the like.

First, an example of a conventional current-driven source driver circuitis shown in FIG. 55, which provides a principle needed to describecurrent-driven source driver IC (source driver circuit) 14 according tothe present invention.

In FIG. 55, reference numeral 551 denotes a D/A converter. The D/Aconverter 551 is fed an n-bit data signal and outputs an analog signalbased on the inputted data. The analog signal enters an operationalamplifier 552, which feeds into an N-channel transistor 471 a. Currentflowing through the N-channel transistor 471 a flows to a resister 531.A terminal voltage of the register R provides a negative input to theoperational amplifier 552. The voltage at the negative terminal equalsthe voltage at the positive terminal of the operational amplifier 552.Thus, the output voltage of the D/A converter 551 equals the terminalvoltage of the resister 531.

If the resistance of the resister 531 is 1 MΩ and the output of the D/Aconverter 551 is 1 (V), a current of 1 (V)/1 MΩ=1 (μA) flows through theresister 531, forming a constant current circuit. Thus, analog output ofthe D/A converter 551 varies with the value of data signal, and apredetermined current flows through the resister 531 according to theanalog output to provide a programming current Iw.

However, the D/A converter circuit 551 has a large circuit scale. Sodoes the operational amplifier 552. Formation of the D/A convertercircuit 551 and operational amplifier 552 in a single output circuitresults in a huge source driver IC 14, which is practically impossibleto build.

The present invention has been made in view of the above point. Thesource driver circuit 14 according to the present invention has acircuit configuration and layout configuration which reduces the scaleof a current output circuit and minimizes variations in output currentamong current output terminals.

FIG. 47 is a block diagram showing a current-driven source driver IC(circuit) 14 according to one example of the present invention. FIG. 47shows a multi-stage current mirror circuit comprising three-stagecurrent sources (471, 472, 473).

In FIG. 47, the current value of the current source 471 in the firststage is copied by the current mirror circuit to N current sources 472in the second stage (where N is an arbitrary integer). The currentvalues of the second-stage current sources 472 are copied by the currentmirror circuit to M current sources 473 in the third stage (where M isan arbitrary integer). Consequently, this configuration causes thecurrent value of the first-stage current source 471 to be copied to N×Mthird-stage current sources 473.

For example, when driving the source signal lines 18 with one sourcedriver IC 14, there are 176 outputs (because the source signal linesrequire a total of 176 outputs for R, G, and B). Here it is assumed thatN=16 and M=11. Thus, 16×11=176 and the 176 outputs can be covered. Inthis way, by using a multiple of 8 or 16 for N or M, it becomes easierto lay out and design the current sources of the driver IC.

The current-driven source driver IC (circuit) 14 employing themulti-stage current mirror circuit according to the present inventioncan absorb variations in transistor characteristics because it has thesecond-stage current sources 472 in between instead of copying thecurrent value of the first-stage current source 471 directly to N×Mthird-stage current sources 473 using the current mirror circuit.

In particular, the present invention is characterized in that afirst-stage current mirror circuit (current source 471) and second-stagecurrent mirror circuits (current sources 472) are placed close to eachother. If a first-stage current source 471 are connected withthird-stage current sources 473 (i.e., in the case of two-stage currentmirror circuit), the second-stage current sources 473 connected to thefirst-stage current source are large in number, making it impossible toplace the first-stage current source 471 and third-stage current sources473 close to each other.

The source driver circuit 14 according to the present invention copiesthe current value of the first-stage current mirror circuit (currentsource 471) to the second-stage current mirror circuits (current sources472), and the current values of the second-stage current mirror circuits(current sources 472) to the third-stage current mirror circuits(current sources 473). With this configuration, the second-stage currentmirror circuits (current sources 472) connected to the first-stagecurrent mirror circuit (current source 471) are small in number. Thus,the first-stage current mirror circuit (current source 471) andsecond-stage current mirror circuits (current sources 472) can be placedclose to each other.

If transistors composing the current mirror circuits can be placed closeto each other, naturally variations in the transistors are reduced, andso are variations in current values. The number of the third-stagecurrent mirror circuits (current sources 473) connected to thesecond-stage current mirror circuits (current sources 472) are reducedas well. Consequently, the second-stage current mirror circuits (currentsources 472) and third-stage current mirror circuits (current sources473) can be placed close to each other.

That is, transistors in current receiving parts of the first-stagecurrent mirror circuit (current source 471), second-stage current mirrorcircuits (current sources 472) and third-stage current mirror circuits(current sources 473) can be placed close to each other on the whole. Inthis way, transistors composing the current mirror circuits can beplaced close to each other, reducing variations in the transistors andgreatly reducing variations in current signals from output terminals.

In the present invention, the terms “current sources 471, 472, and 473”and “current mirror circuits” are used interchangeably. That is, currentsources are a basic construct of the present invention and the currentsources are embodied into current mirror circuits. Thus, a currentsource is not limited to a current mirror circuit and may be a constantcurrent circuit consisting of a combination of a operational amplifier552, transistor 471, and register R.

FIG. 48 is a structural drawing of a more concrete source driver IC(circuit) 14. It illustrates part of third current sources 473. This isan output part connected to one source signal line 18. It is composed ofmultiple current mirror circuits (unit transistors 484 (1 unit)) of thesame size as a current mirror configuration in the final stage. Theirnumber is bit-weighted according to the data size of image data.

Incidentally, the transistors composing the source driver IC (circuit)14 according to the present invention are not limited to a MOS type andmay be a bipolar type. Also, they are not limited to siliconsemiconductors and may be gallium arsenide semiconductors. Also, theymay be germanium semiconductors. Alternatively, they may be formeddirectly on a substrate-using low-temperature polysilicon technology,other polysilicon technology, or amorphous silicon technology.

FIG. 48 illustrates an example of the present invention which handles6-bit digital input. Six bits are the sixth power of two, and thusprovide a 64-gradation display. This source driver IC 14, when mountedon an array board, provides 64 gradations each of red (R), green (G),and blue (B), meaning 64×64×64=approximately 260,000 colors.

Sixty-four (64) gradations require 1 D0-bit unit transistor 484, twoD1-bit unit transistors 484, four D2-bit unit transistors 484, eightD3-bit unit transistors 484, sixteen D4-bit unit transistors 484, andthirty-two D5-bit unit transistors 484 for a total of 63 unittransistors 484. Thus, the present invention produces one output usingas many unit transistors 484 as the number of gradations (64 gradationsin this example) minus 1. Incidentally, even if one unit transistor isdivided into a plurality of sub-unit transistors, this simply means thata unit transistor is divided into sub-unit transistors, and makes nodifference in the fact that the present invention uses as many unittransistors as the number of gradations minus 1.

In FIG. 48, D0 represents LSB input and D5 represents MSB input. When aD0 input terminal is high (positive logic) a switch 481 a is closed (theswitch 481 a is an on/off means and may be constructed of a singletransistor or may be an analog switch consisting of a P-channeltransistor and N-channel transistor. Then, current flows to a currentsource (single-unit) 484 composing a current mirror. The current flowsthrough internal wiring 483 in the IC 14. Since the internal wiring 483is connected to the source signal line 18 via a terminal electrode ofthe IC 14, the current flowing through internal wiring 483 provides aprogramming current for the pixels 16.

For example, when a D1 input terminal is high (positive logic), a switch481 b is closed. Then, current flows to two current sources(single-unit) 484 composing a current mirror. The current flows throughthe internal wiring 483 in the IC 14. Since the internal wiring 483 isconnected to the source signal line 18 via a terminal electrode of theIC 14, the current flowing through internal wiring 483 provides aprogramming current for the pixels 16.

The same applies to the other switches 481. When a D2 input terminal ishigh (positive logic), a switch 481 c is closed. Then, current flows tofour current sources (single-unit) 484 composing a current mirror. Whena D5 input terminal is high (positive logic), a switch 481 f is closed.Then, current flows to 32 (thirty-two) current sources (single-unit) 484composing a current mirror.

In this way, based on external data (D0 to D5), current flows to thecorresponding current sources (single-unit). That is, current flows to 0to 63 current sources (single-unit) depending on the data.

Incidentally, for ease of explanation, it is assumed that there are 63current sources for a 6-bit configuration, but this is not restrictive.In the case of 8-bit configuration, 255 unit transistors 484 can beformed (placed). For a 4-bit configuration, 15 unit transistors 484 canbe formed (placed). The transistors 484 constituting the unit currentsources have a channel width W and channel width L. The use of equaltransistors makes it possible to construct output stages with smallvariations.

Besides, not all the unit transistors 484 need to pass equal current.For example, individual unit transistors 484 may be weighted. Forexample a current output circuit may be constructed using a mixture ofsingle-unit unit transistors 484, double-sized unit transistors 484,quadruple-sized unit transistors 484, etc. However, if unit transistors484 are weighted, the weighted current sources may not provide the rightproportions, resulting in variations. Thus, even when using weighting,it is preferable to construct each current source from transistors eachof which corresponds to a single-unit current source.

The unit transistor 484 should be equal to or larger than a certainsize. The smaller the transistor size, the larger the variations inoutput current. The size of a transistor 484 is given by the channellength L multiplied by the channel width W. For example, if W=3 μm andL=4 μm, the size of the unit transistor 484 constituting a unit currentsource is W×L=12 square μm. It is believed that crystal boundaryconditions of silicon wafers have something to do with the fact that asmaller transistor size results in larger variations. Thus, variationsin output current of transistors are small when each transistor isformed across a plurality of crystal boundaries.

Relationship between size of transistors and variations in outputcurrent is shown in FIG. 119. The horizontal axis of the graph in FIG.119 represents transistor size (square μm). The vertical axis representsvariations in output current in percentage terms. The variations (%) inoutput current here were determined using groups of 63 unit currentsources (unit transistors) 484 formed on a wafer. Thus, although thehorizontal axis of the graph represents the size of a transistor (sizeof a unit transistor 484) constituting one current source, since thereare actually 63 transistors connected in parallel, the total area of thetransistors is 63 times larger. However, FIG. 119 is based on the sizeof a unit transistor 484. Thus, FIG. 119 shows that variations in theoutput current of 63 unit transistors 484 with an area of 30 square μmeach is 0.5%.

In the case of 64 gradations, 100/64=1.5%. Thus, the variations in theoutput current must be within 1.5%. From FIG. 119, it can been seen thatin order for the variations to be within 1.5%, the size of the unittransistor must be equal to or larger than 2 square μm (in the case of64 gradations, sixty-three 2-square μm unit transistors operate) On theother hand, there are limits to transistor size because largertransistors increase the size of an IC chip and there are limits to thewidth per one output. In this respect, the upper limit to the size ofthe unit transistor 484 is 300 square μm. Thus, in the case of 64gradations, the size of the unit transistor 484 must be from 2 square μmto 300 square μm (both inclusive) In the case of 128 gradations,100/128=1%. Thus, the variations in the output current must be within1%. From FIG. 119, it can been seen that in order for the variations tobe within 1%, the size of the unit transistor must be equal to or largerthan 8 square μm. Thus, in the case of 128 gradations, the size of theunit transistor 484 must be from 8 square μm to 300 square μm (bothinclusive).

Generally, if the number of gradations is K and the size of a unittransistor 484 is St (square μm), the following relationship should besatisfied:40≦K/{square root}{square root over ( )}(St) and St≦300

More preferably, the following relationship should be satisfied:120≦K/{square root}{square root over ( )}(St) and St≦300

In the above example 64 gradations are represented by 63 transistors.When representing 64 gradations by 127 unit transistors 484, theunit-transistor 484 size is the total size of two unit transistors 484.For example, in the case where 64 gradations are represented by 127 unittransistors 484, if the size of a unit transistor 484 is 10 square μm,the unit-transistor 484 size is given in FIG. 119 as 1×2=20. Similarly,in the case where 64 gradations are represented by 255 unit transistors484, if the size of a unit transistor 484 is 10 square μm, theunit-transistor 484 size is given in FIG. 119 as 10×4=40.

It is necessary to take into consideration not only the size, but alsothe shape of the unit transistor 484. This is to reduce kink effect. Akink is a phenomenon in which current flowing through a unit transistor484 changes when the voltage between the source (S) and drain (D) of theunit transistor 484 is varied with the gate voltage of the unittransistor 484 kept constant. In the absence of kink effect (in idealstate), the current flowing through the unit transistor 484 does notchange even if the voltage applied between the source (S) and drain (D)of the unit transistor 484 is varied.

Kink effect occurs when the source signal lines 18 vary due tovariations in Vt of driver transistors 11 a shown in FIG. 1 and thelike. The driver circuit 14 passes programming current through thesource signal line 18 so that the programming current will flow throughthe driver transistor 11 a of the pixel. The programming current causeschanges in the gate terminal voltage of the driver transistor 11 a, andconsequently the programming current flows through the driver transistor11 a. As can be seen From FIG. 3, when a selected pixel 16 is inprogramming mode, the gate terminal voltage of the driver transistor 11a equals the potential of the source signal line 18.

Thus, the potentials of the source signal lines 18 vary due tovariations in Vt of the driver transistors 11 a in pixels 16. Thepotential of a source signal line 18 equals the source-drain voltage ofthe unit transistor 484 of the driver circuit 14. That is, variations inVt of the driver transistors 11 a in the pixels 16 cause thesource-drain voltage applied to the unit transistors 484 to vary. Then,the source-drain voltage causes variations in the output voltage of theunit transistor 484 due to kinks.

FIG. 123 is a graph showing deviation (variation) in L/W of unittransistors from a target value. When the L/W ratio of unit transistorsis equal to smaller than 2, the deviation from the target value is large(the slope of the straight line is large). However, as L/W increases,the deviation from the target value tends to decrease. When L/W of unittransistors is equal to larger than 2, the deviation from the targetvalue is small. Also, the deviation from the target value is 0.5% orless when L/W=2 or more. Thus, this value can be used for source drivercircuits 14 to indicate accuracy of transistors. Incidentally, L is thechannel length of the unit transistor 484 and W is the channel width ofthe unit transistor 484.

However, it is not that the channel length L of the unit transistor 484can be increased indefinitely. The larger the channel length L, thelarger the IC chip 14. Also, a large channel length L leads to increasedgate terminal voltage in the unit transistor 484, increasing the powersupply voltage required for the source driver IC 14. Increased powersupply voltage involves the use of a highly voltage resistant ICprocess. A source driver IC 14 produced by a voltage resistant ICprocess leads to large variations in the output of the unit transistor484 (see FIG. 121 and its description). Results of analysis indicatethat preferably L/W should be 100 or less. More preferably, it should be50 or less.

In view of the above circumstances, it is preferable that L/W of a unittransistor is two or more. Also, preferably L/W is 100 or less. Morepreferably, L/W is 40 or less.

Besides, L/W also depends on the number of gradations. If the number ofgradations is small, there is no problem even if there are variations inthe output current of the unit transistor 484 due to kink effect becausethere are large differences between gradations. However, in the case ofa display panel with a large number of gradations, since there are smalldifferences between gradations, even small variations in the outputcurrent of the unit transistor 484 due to kink effect will decrease thenumber of gradations.

In view of the above circumstances, the driver circuit 14 according tothe present invention is configured to satisfy the followingrelationship:({square root}{square root over ( )}(K/16))≦L/W≦ and ({squareroot}{square root over ( )}(K/16))×20where K is the number of gradations, L is the channel length of the unittransistor 484, and W is the channel width of the unit transistor. Thisrelationship is illustrated in FIG. 120. The area above the straightline in FIG. 120 is relevant to the present invention.

The variations in the output current of the unit transistor 484 alsodepend on the voltage resistance of the source driver IC 14. The voltageresistance of the source driver IC generally means the power supplyvoltage of the IC. For example, voltage resistance of 5 V means the useof the power supply voltage at a standard voltage of 5 V. Incidentally,IC voltage resistance can translate into maximum working voltage.Semiconductor IC makers have standardized voltage-resistance processessuch as a 5-V voltage-resistance process and 10-V voltage-resistanceprocess.

It is believed that film properties and film thickness of a gateinsulating film of the unit transistor 484 have something to do with thefact that IC voltage resistance affects variations in the output currentof the unit transistor 484. The transistors produced in a process withhigh IC voltage resistance have a thick gate insulating film. This isintended to avoid dielectric breakdown even under application of a highvoltage. A thick gate insulating film makes its control difficult andincreases variations in its film properties. This increases variationsin the transistors. Also, the transistors produced in a highvoltage-resistance process have low mobility. With low mobility, evenslight changes in electrons injected into transistor gates cause changesin characteristics. This increases variations in the transistors. Toreduce variations in the unit transistors 484, it is preferable to adoptan IC process with low IC voltage resistance.

FIG. 121 illustrates relationship between IC voltage resistance andoutput variations of unit transistors 484. The variation rate on thevertical axis is based on the variation of unit transistors 484 producedin a 1.8-V voltage resistance process, which variation is taken to be 1.FIG. 121 shows output variations of unit transistors 484 which wereproduced in various IC voltage resistance processes and have a shape ofL/W=12/6 (μm). A plurality of unit transistors 484 were produced in eachIC voltage resistance process and variations in their output currentwere determined. The voltage resistance processes were composeddiscretely of 1.8-V voltage resistance, 2.5-V voltage resistance, 3.3-Vvoltage resistance, 5-V voltage resistance, 8-V voltage resistance, and10-V voltage resistance, 15-V voltage resistance processes. However, forease of explanation, variations in the transistors formed in thedifferent voltage resistance processes are plotted on the graph andconnected with straight lines.

As can be seen from FIG. 121, the variation rate (variations in theoutput current of the unit transistors 484) increases gradually up untilan IC voltage resistance of 9 V. However, when the IC voltage resistanceexceeds 10 V, the slope of the variation rate with respect to the ICvoltage resistance becomes large.

In FIG. 121, the permissible limit to the variation rate is 3 for 64- to256-gradation display. The variation rate varies with the area, L/W,etc. of the unit transistor 484. However, the variation rate withrespect to the IC voltage resistance is hardly affected by the shape ofthe unit transistor 484. The variation rate tends to increase above anIC voltage resistance of 9 to 10 V.

On the other hand, the potential at an output terminal 681 in FIG. 48varies with the programming current in the driver transistor 11 a of thepixel 16. The gate terminal voltage of the driver transistor 11 a isapproximately equal to the potential of the source signal line 18. Also,the source signal line 18 and the output terminal 681 of the sourcedriver IC (circuit) 14 are equal in potential. When the drivertransistor 11 a of the pixel 16 passes white raster (maximum whitedisplay) current, its gate terminal voltage is designated as Vw. Whenthe driver transistor 11 a of the pixel 16 passes black raster(completely black display) current, its gate terminal voltage isdesignated as Vb. The absolute value of Vw−Vb must be 2 V or larger.When the voltage Vw is applied to the output terminal 681, inter-channelvoltage of the unit transistor 484 must be 0.5 V or higher.

Thus, a voltage of 0.5 V to ((Vw−Vb)+0.5) V is applied to the outputterminal 681 (during current programming, the gate terminal voltage ofthe driver transistor 11 a of the pixel 16 is applied to the outputterminal 681, which is connected with the source signal line 18). SinceVw−Vb equals 2 V, a voltage of up to 2 V+0.5 V=2.5 V is applied to theoutput terminal 681. Thus, even if the output voltage (current) of thesource driver IC 14 is based on a rail-to-rail circuit configuration(circuit configuration capable of outputting a voltage up to the ICpower supply voltage), the IC voltage resistance must be 2.5V. Theamplitude required by a terminal 741 is 2.5 V or more.

Thus, it is preferable to use a voltage resistance process in the rangeof 2.5-V to 10-V (both inclusive) for the source driver IC 14. Morepreferably, a voltage resistance process in the range of 3-V to 9-V(both inclusive) is used for the source driver IC 14.

Incidentally, it has been described that a voltage resistance process inthe range of 2.5-V to 10-V (both inclusive) is used for the sourcedriver IC 12. This voltage resistance is also applied to examples (e.g.,a low-temperature polysilicon process) in which the source drivercircuit 14 is formed directly on an array board 71. Working voltageresistance of a source driver circuit 14 formed directly on an arrayboard 71 can be high and exceeds 15 V in some cases. In such cases, thepower supply voltage used for the source driver circuit 14 may besubstituted with the IC voltage resistance illustrated in FIG. 121.Also, the source driver IC 14 may have the IC voltage resistancesubstituted with the power supply voltage used.

The area of a unit transistor 484 is correlated with the variations inits output current. FIG. 122 is a graph obtained by varying thetransistor width W of a unit transistor 484 with the area of the unittransistor 484 kept constant. In FIG. 121, the variation of the unittransistor 484 with a channel width W of 2 μm is taken as 1. Thevertical axis of the graph represents a relative proportion, where thevariation which occurs when the channel width W is 2 μm is taken as 1.

As can be seen from FIG. 122, the variation rate increases graduallywhen W of the unit transistor 484 is from 2 μm to 9 or 10 μm. Theincrease in the variation rate tends to become large when W is 10 μm ormore. Also, the variation rate tends to increase when the channel widthW=2 μm or less.

In FIG. 122, the permissible limit to the variation rate is 3 for 64- to256-gradation display. The variation rate varies with the area of theunit transistor 484. However, the variation rate with respect to the ICvoltage resistance is hardly affected by the area of the unit transistor484.

Thus, preferably, the channel width W of the unit transistor 484 is from2 μm to 10 μm (both inclusive). More preferably, the channel width W ofthe unit transistor 484 is from 2 μm to 9 μm (both inclusive). However,when the number of gradations is 64, a channel width W of 2 μm to 15 μm(both inclusive) is practically acceptable.

As illustrated in FIG. 52, current flowing through second-stage currentmirror circuits 472 b is copied to transistors 473 a which composethird-stage current mirror circuits. If a current mirror ratio is 1, thecurrent flows through transistors 473 b. The current is copied to theunit transistor 484 in the final stage.

D0, which is provided by one unit transistor 484, provides the value ofthe current flowing through the unit transistor 473 of the final-stagecurrent source. D1, which is provided by two unit transistors 484,provides a two times larger current value than the final-stage currentsource. D2, which is provided by four unit transistors 484, provides afour times larger current value than the final-stage current source; andD5, which is provided by 32 unit transistors 484, provides a 32 timeslarger current value than the final-stage current source. The above isbased on the assumption that the mirror ratio of the final-stage currentmirror circuits is 1.

Programming current Iw is output (drawn) to the source signal line viaswitches controlled by 6-bit image data consisting of D0, D1, D2, . . ., and D5. Thus, according to activation and deactivation of the 6-bitimage data consisting of D0, D1, D2, . . . , and D5, currents 1 time, 2times, 4 times, and/or 32 times as large as the final-stage currentsource 473 are added and outputted to the output line. That is,according to activation and deactivation of the 6-bit image dataconsisting of D0, D1, D2, . . . , and D5, 0 to 63 times as large acurrent as the final-stage current source 473 is output from the outputline (the current is drawn from the source signal line 18.

Actually, as illustrated in FIGS. 76, 77, 78, and 118, in the sourcedriver IC 14, reference currents (IaR, IaG, and IaB) for R, G, and B,respectively, can be adjusted by registers 491 (491R, 491G, and 491B).By adjusting the reference currents Ia, the white balance can beadjusted easily.

In order to achieve full-color display on an EL display panel, it isnecessary to provide a reference current for each of R, G, and B. Thewhite balance can be adjusted by controlling the ratios of the RGBreference currents. In the case of current driving as well as thepresent invention, the value of current passed by the unit transistor484 is determined based on one reference current. Thus, the currentpassed by the unit transistor 484 can be determined by determining themagnitude of the reference current. Consequently, the white balance inevery gradation can be achieved by setting a reference current for eachof R, G, and B. The above matters work because the source driver circuit14 produces current outputs varied in steps (is current-driven). Thus,the point is how the magnitude of the reference current can be set foreach of R, G, and B.

The light emission efficiency of an EL element is determined by, ordepends heavily on, the thickness of a film vapor-deposited or appliedto the EL element. The film thickness is almost constant within eachlot. Through lot control of the film thickness of the EL element 15, itis possible to determine relationship between the current passed throughthe EL element 15 and light emission efficiency. That is, the currentvalue used for white balancing is fixed for each lot.

FIG. 49 is an exemplary circuit diagram showing 176 outputs (N×M=176) ofa three-stage current mirror circuit. In FIG. 49, the current source 471constituted of the first-stage current mirror circuit is referred to asa parent current source, the current sources 472 constituted of thesecond-stage current mirror circuits are referred to as child currentsources, and the current sources 473 constituted of the third-stagecurrent mirror circuits are referred to as grandchild current sources.

The use of an integral multiple for the third-stage current mirrorcircuits which are the final-stage current mirror circuits makes itpossible to minimize variations in the 176 outputs and producehigh-accuracy current outputs.

Incidentally, dense placement means placing the first current source 471and the second current sources 472 (the current or voltage output andcurrent or voltage input) at least within a distance of 8 mm. Morepreferably, they are placed within 5 mm. It has been shown analyticallythat when placed at this density, the current sources can fit into asilicon chip with little difference in transistor characteristics (Vtand mobility (μ)). Similarly, the second current sources 472 and thirdcurrent sources 473 (the current output and current input) are placed atleast within a distance of 8 mm. More preferably, they are placed within5 mm. Needless to say, the above items also apply to other examples ofthe present invention.

The current or voltage output and current or voltage input mean thefollowing relationships. In the case of voltage-based delivery shown inFIG. 50, the transistor 471 (the output) of the (I)-th current sourceand the transistor 472 a (the input) of the (I+1)-th current source areplaced close to each other. In the case of current-based delivery shownin FIG. 51, the transistor 471 a (the output) of the (I)-th currentsource and the transistor 472 b (the input) of the (I+1)-th currentsource are placed close to each other.

Incidentally, although it is assumed in FIGS. 49, 50, etc. that there isone transistor 471, this is not restrictive. For example, it is alsopossible to form a plurality of small sub-transistors 471 and connectthe source or drain terminals of the sub-transistors with the register491 to form a unit transistor 484. By connecting the plurality of smallsub-transistors in parallel, it is possible to reduce variations of theunit transistor 484.

Similarly, although it is assumed that there is one transistor 472 a,this is not restrictive. For example, it is also possible to form aplurality of small sub-transistors 472 a and connect the gate terminalsof the transistors 472 a with the gate terminal of the transistor 471.By connecting the plurality of small transistors 472 a in parallel, itis possible to reduce variations of the transistor 472 a.

Thus, according to the present invention, the following configurationscan be illustrated: a configuration in which one transistor 471 isconnected with a plurality of transistors 472 a, a configuration inwhich a plurality of transistors 471 are connected with one transistor472 a, and a configuration in which a plurality of transistors 471 areconnected with a plurality of transistors 472 a. These examples will bedescribed in more detail below.

The above items also apply to a configuration of transistors 473 a and473 b in FIG. 52 in FIG. 52. Possible configurations include aconfiguration in which one transistor 473 a is connected with aplurality of transistors 473 b, a configuration in which a plurality oftransistors 473 a are connected with one transistor 473 b, and aconfiguration in which a plurality of transistors 473 a are connectedwith a plurality of transistors 473 b. By connecting the plurality ofsmall transistors 473 in parallel, it is possible to reduce variationsof the transistor 473.

The above items also apply to relationship between transistors 472 a and472 b in FIG. 52. Also, preferably a plurality of transistors 473 b areused in FIG. 48. Similarly, it is preferable to use plurality oftransistors 473 in FIGS. 56 and 57.

Although it has been stated that the source driver IC 14 consists of asilicon chip, this is not restrictive. The source driver IC 14 may beconstructed of another semiconductor chip formed on a gallium substrateor germanium substrate. Also, the unit transistor 484 may be a bipolartransistor, CMOS transistor, FET, Bi-CMOS transistor, or DMOStransistor. However, in terms of reducing variations in the output ofthe unit transistor 484, preferably a CMOS transistor is used for theunit transistor 484.

Preferably, the unit transistor 484 is an N-channel transistor. The unittransistor consisting of a P-channel transistor has 1.5 times largeroutput variations than the unit transistor consisting of an N-channeltransistor.

Since it is preferable that the unit transistor 484 of the source driverIC 14 is an N-channel transistor, the programming current of the sourcedriver IC 14 is a current drawn from the pixel 16. Thus, the drivertransistor 11 a of the pixel 16 is a P-channel transistor. The switchingtransistor 11 d in FIG. 1 is also a P-channel transistor.

Thus, the configuration in which the unit transistor 484 in the outputstage of the source driver IC (circuit) 14 is an N-channel transistorand the driver transistor 11 a of the pixel 16 is a P-channel transistoris characteristic of the present invention. Incidentally, it ispreferable that all the transistors (transistors 11 a, 11 b, 11 c, and11 d) composing the pixel 16 are P-channel transistors. This eliminatesthe process of forming N-channel transistors, resulting in low costs andhigh yields.

Incidentally, although it has been stated that the unit transistor 484is formed in the IC 14, this is not restrictive. The source drivercircuit 14 may be formed by low-temperature polysilicon technology. Inthat case again, it is preferable that the unit transistors 484 in thesource driver circuit 14 are N-channel transistors.

FIG. 51 shows an example of configuration for current-based delivery.FIG. 50 also shows an example of configuration for current-baseddelivery. FIGS. 50 and 51 are similar in terms of circuit diagrams anddiffer in layout configuration, i.e., wiring layout. In FIG. 50,reference numeral 471 denotes a first-stage N-channel current sourcetransistor, 472 a denotes a second-stage N-channel current sourcetransistor, and 472 b denotes a second-stage P-channel current sourcetransistor.

In FIG. 51, reference numeral 471 a denotes a first-stage N-channelcurrent source transistor, 472 a denotes a second-stage N-channelcurrent source transistor, and 472 b denotes a second-stage P-channelcurrent source transistor.

In FIG. 50, the gate voltage of the first-stage current sourceconsisting of a variable register 491 (used to vary current) and theN-channel transistor 471 is delivered to the gate of the N-channeltransistor 472 a of the second-stage current source. Thus, this is alayout configuration of a voltage-based delivery type.

In FIG. 51, the gate voltage of the first-stage current sourceconsisting of a variable register 491 and the N-channel transistor 471 ais applied to the gate of the N-channel transistor 472 a of the adjacentsecond-stage current source, and consequently the value of the currentflowing through the transistor is delivered to the P-channel transistor472 b of the second-stage current source. Thus, this is a layoutconfiguration of a current-based delivery type.

Incidentally, although this example of the present invention focuses onrelationship between the first current source and second current sourcefor ease of explanation or understanding, this is not restrictive and itgoes without saying that this example also applies (can be applied) torelationship between the second current source and third current sourceas well as relationship between other current sources.

In the layout configuration of the current mirror circuit of thevoltage-based delivery type shown in FIG. 50, the N-channel transistor471 of the first-stage current source and the N-channel transistor 472 aof the second-stage current source composing the current mirror circuitare separated (or liable to get separated, to be precise), and thus thetwo transistors tend to differ in characteristics. Consequently, thecurrent value of the first-stage current source is not transmittedcorrectly to the second-stage current source and there can bevariations.

In contrast, in the layout configuration of the current mirror circuitof the current-based delivery type shown in FIG. 51, the N-channeltransistor 471 a of the first-stage current source and the N-channeltransistor 472 a of the second-stage current source composing thecurrent mirror circuit are located adjacent to each other (easy to placeadjacent to each other), and thus the two transistors hardly differ incharacteristics. Consequently, the current value of the first-stagecurrent source is transmitted correctly to the second-stage currentsource and there can be little variations.

In view of the above circumstances, it is preferable to use a layoutconfiguration of the current-based delivery type instead of thevoltage-based delivery type for the circuit configuration of themulti-stage current mirror circuit according to the present invention(the source driver IC (circuit) 14 of the current-based delivery typeaccording to the present invention) in terms of reduced variations.Needless to say the above example can be applied to other examples ofthe present invention.

Incidentally, although delivery from the first-stage current source tothe second-stage current source has been cited for the sake ofexplanation, the same applies to delivery from the second-stage currentsource to the third-stage current source, delivery from the third-stagecurrent source to the fourth-stage current source, and soon. Also, itgoes without saying that the present invention may adopt a single-stagecurrent source configuration (see FIGS. 164, 165, 166, etc.)

FIG. 52 shows a current-based delivery version of three-stage currentmirror circuit (three-stage current source) shown in FIG. 49 (which,therefore shows a circuit configuration of a voltage-based deliverytype).

In FIG. 52, a reference current is created first by the variableregister 491 and N-channel transistor 471. Incidentally, although it isstated that the reference current is adjusted by the variable register491, actually the source voltage of the N-channel transistor 471 is setand regulated by an electronic regulator formed (or placed) in thesource driver IC (circuit) 14. Alternatively, the reference current isadjusted by directly supplying the source terminal of the transistor 471with current outputted from a current-type electronic regulatorconsisting of a large number of unit transistors (single-unit) 484 asshown in FIG. 48 (see FIG. 53).

The gate voltage of the first-stage current source constituted of thetransistor 471 is applied to the gate of the N-channel transistor 472 aof the adjacent second-stage current source, and the currentconsequently flowing through the transistor is delivered to theP-channel transistor 472 b of the second-stage current source. Also, thegate voltage of the P-channel transistor 472 b of the second-stagecurrent source is applied to the gate of the N-channel transistor 473 aof the adjacent third-stage current source, and the current consequentlyflowing through the transistor is delivered to the N-channel transistor473 b of the third-stage current source. A large number of unittransistors 484 are formed (placed) at the gate of the N-channeltransistor 473 b of the third-stage current source according to therequired bit count as illustrated in FIG. 48.

The configuration in FIG. 53 is characterized in that the first-stagecurrent source 471 of the multi-stage current mirror circuit is equippedwith a current-value adjustment element. This configuration allowsoutput current to be controlled by varying the current value of thefirst-stage current source 471.

Variations in the Vt of transistors (variations in characteristics) areon the order of 100 mV within a wafer. However, variations in Vt oftransistors formed within 100μ of each other should be 10 mV or less(actual measurement) That is, by configuring a current mirror circuitwith transistors formed close to each other, it is possible to reducevariations in the output current of the current mirror circuit. Thisreduces variations in the output current among terminals of the sourcedriver IC.

Incidentally, although variations in Vt are described as variationsamong transistors, variations among transistors are not limited tovariations in Vt. However, since variations in Vt are a main cause ofvariations among transistors, it is assumed that the variations inVt=the variations among transistors, for ease of understanding.

FIG. 118 shows formation areas of transistors versus variations in theoutput current of unit transistors 484 based on measurement results. Thevariations in the output current are variations in current at athreshold voltage (Vt). Black dots indicate variations in the outputcurrent of evaluation sample transistors (10 to 200 in number) createdin a formation area. There is almost no variation (output currentvariations only within a margin of error, meaning that a constant outputcurrent is produced) in the output current of transistors formed in areaA (a formation area of 0.5 square millimeters or less) in FIG. 118.Conversely, in area C (a formation area of 2.4 square millimeters ormore), variations in the output current with respect to the formationarea tend to increase sharply. In area B (a formation area of 0.5 to 2.4square millimeters), variations in the output current are almostproportional to the formation area.

However, the absolute value of output current varies from wafer towafer. However, this problem can be dealt with by adjusting thereference voltage or setting it to a fixed value in the source drivercircuit (IC) 14 of the present invention. Also, it can be dealt with(solved) by modifying the current mirror circuit ingeniously.

The present invention varies (controls) the amount of current flowingthrough the source signal line 18 by switching the number of currentsflowing through the unit transistors 484 using input digital data (D).When the number of gradations is 64 or more, since 1/64=0.015,theoretically variations in output current should be within 1 to 2%.Incidentally, output variations within 1% are difficult to distinguishvisually and output variations of 0.5% or below are impossible todistinguish (look uniform).

To keep output current variations (%) within 1%, the formation area of atransistor group (the transistors among which variations should besuppressed) should be kept within 2 square millimeters as indicated bythe results shown in FIG. 118. More preferably, the output currentvariations (i.e., variations in the Vt of transistors) should be keptwithin 0.5%. That is, the formation area of a transistor group 521 canbe kept within 1.2 square millimeters as indicated by the results shownin FIG. 118. Incidentally, the formation area is given by the verticallength multiplied by the horizontal length. For example, a formationarea of 1.2 square millimeters results from 1 mm×1.2 mm.

The same applies to a set of unit transistors 484 (a block of 63transistors 484 in the case of 64 gradations, see FIG. 48, etc.). Theformation area of the set of unit transistors 484 should be kept within2 square millimeters. More preferably, the formation area of the set ofunit transistors 484 should be kept within 1.2 square millimeters.

Incidentally, the above applies to 8-bit (256 gradations) or largerdata. For a smaller number of gradations, for example, in the case of6-bit data (64 gradations), variations in output current may besomewhere around 2% (virtually no problem in terms of image display). Inthis case, the formation area of a transistor group 521 can be keptwithin 5 square millimeters. There is no need for the two transistorgroups 521 (transistor groups 521 a and 521 b are shown in FIG. 52) tosatisfy this condition. Effect of the present invention can be achievedif at least one of the transistor groups (one or more transistor groups521 if there are more than three) satisfy the condition. Preferably,this condition should be satisfied for a lower level transistor group521 (521 a is higher than 521 b). This will reduce image displayproblems.

In the source driver circuit (IC) 14 of the present invention, aplurality of current sources consisting of parent, child, and grandchildcurrent sources are connected in multiple stages (of course there may betwo stages consisting of parent and child current sources) and placeddensely, as shown in FIG. 52. Current-based delivery is made betweencurrent sources (between the transistor groups 521). Specifically,transistors enclosed by dotted lines in FIG. 52 (transistor groups 521)are placed densely. The transistor groups 521 make voltage-baseddelivery between each other. The parent current source 471 and childcurrent sources 472 a are formed (placed) approximately in the center ofthe source chip. This makes it possible to relatively shorten thedistance between the transistors 472 a composing the child currentsources placed on the left and right of the chip and the transistors 472b composing current child sources. That is, the top-level transistorgroup 521 a is placed at the approximate center of the IC chip. Then,lower-level transistor groups 521 b are placed on the left and right ofthe IC chip 14. Preferably, the transistors are placed, formed, orproduced in such a way that approximately equal numbers of lower-leveltransistor groups 521 b will be on the left and right of the IC chip 14.Incidentally, the above items are not limited to IC chips 14, but applyto source driver circuits 14 formed directly on array boards 71 usinglow-temperature polysilicon technology or high-temperature polysilicontechnology. The same is true of the other items.

According to the present invention, one transistor group 521 a isconstructed, placed, formed, or built at the approximate center of theIC chip 14 and eight transistor groups 521 b each are formed on the leftand right of the chip (N=8+8, see FIG. 47). Preferably the childtransistor groups 521 b are arranged in such a way that their numberswill be equal on the left and right of the chip or that the differencebetween the number of the child transistor groups 521 b formed or placedon the left with respect to the center of the chip where the parent isformed and the number of the child transistor groups 521 b formed orplaced on the right of the chip will be four or less. More preferably,the difference between the number of the child transistor groups 521 bformed or placed on the left of the chip and the number of the childtransistor groups 521 b formed or placed on the right of the chip is oneor less. The above items similarly apply to grandchild transistor groups(omitted in FIG. 52).

Voltage-based delivery (voltage connection) is made between the parentcurrent source 471 and child current sources 472 a. Consequently, tendsto be affected by variations in the Vt of the transistors. Thus, thetransistors in the transistor group 521 a are placed densely. Theformation area of the transistor group 521 a is kept within 2 squaremillimeters. More preferably, it is kept within 1.2 square millimetersas shown in FIG. 118. If the number of gradations is 64 or less, ofcourse, the formation area may be within 5 square millimeters.

Data is delivered between the transistor group 521 a and childtransistors 472 b via current, and thus the current may flow somedistance. Regarding the distance (e.g., between the output terminals ofthe higher-level transistor group 521 a and input terminals of thelower-level transistor group 521 b) the transistors 472 a composing thesecond current sources (child) and the transistors 472 b composing thesecond current sources (child) should be placed at least within 10 mm ofeach other as described above. Preferably, the transistors should beplaced or formed within 8 mm. More preferably, they should be placedwithin 5 mm.

It has been shown analytically that differences in characteristics (Vtand mobility (μ)) of transistors placed in a silicon chip do not havemuch impact in the case of current-based delivery if the distance iswithin this range. Preferably, the above conditions are satisfiedespecially by lower-level transistor groups. For example, if thetransistor group 521 a is at the top level with the transistor groups521 b lying below it and transistor groups 521 c lying further belowthem, the current-based delivery between the transistor groups 521 b andtransistor groups 521 c should satisfy the above conditions. Thus,according to the present invention it is not always necessary that allthe transistor groups 521 satisfy the above conditions. It is sufficientthat at least a pair of transistor groups 521 satisfy the aboveconditions. This is because the lower the level, the more transistorgroups 521 there are.

This similarly applies to the transistors 473 a constituting the third(grandchild) current sources and transistors 473 b constituting thethird current sources. Needless to say, almost the same applies tovoltage-based delivery.

The transistor groups 521 b are formed, built, or placed in theleft-to-right direction of the chip (in the longitudinal direction,i.e., at locations facing the output terminal 681). The transistorgroups 521 b are formed, built, or placed in the left-to-right directionof the chip (in the longitudinal direction, i.e., at locations facingthe output terminal 681). According to the present invention, the numberM of the transistor groups 521 b is 11 (see FIG. 47).

Voltage-based delivery (voltage connection) is made between the childcurrent sources 472 b and grandchild current sources 473 a. Thus, thetransistors in the transistor groups 521 b are placed densely as is thecase with the transistor group 521 a. The formation area of thetransistor group 521 b should be within 2 square millimeters as shown inFIG. 118. More preferably, it should be within 1.2 square millimeters.However, even slight variations in the Vt of the transistors in thetransistor groups 521 b tend to appear on the screen. Thus, preferablythe formation area should be area A (0.5 square millimeters or less) inFIG. 118.

Data is delivered between the grandchild transistors 473 a andtransistors 473 b (current-based delivery), and thus the current mayflow some distance in the transistor group 521 b. The description ofdistances provided earlier applies here as well. The transistors 473 aconstituting the third (grandchild) current sources and transistors 473b constituting the second (grandchild) current sources should be placedwithin at least 8 mm of each other. More preferably, they should beplaced within 5 mm.

FIG. 53 shows the current-value adjustment element constituted of anelectronic regulator. The electronic regulator consists of a resister531 (which is formed of polysilicon, controls current, and createsreference voltages), decoder circuit 532, level-shifter circuit 533,etc. Incidentally, the electronic regulator outputs current. Atransistor 481 functions as an analog switch circuit.

Incidentally, in the source driver IC (circuit) 14, transistors may bereferred to as current sources. This is because transistors function ascurrent sources in current mirror circuits and the like composed oftransistors.

Electronic regulators circuits are formed (or placed) according to thenumber of colors used by the EL display panel. For example, if the threeprimary colors RGB are used, preferably three electronic regulators areformed (or placed) corresponding to the colors so that the colors can beadjusted independently. However, if one color is used as a reference (isfixed), as many electronic regulators circuits as the number of colorsminus 1 should be formed (or placed).

FIG. 68 shows a configuration in which resistive elements 491 are formed(or placed) to control reference voltages of the three primary colorsRGB independently. Of course, it goes without saying that the resistiveelements 491 may be substituted with electronic regulators. Also,resistive elements 491 may be built into the source driver IC (circuit)14. Basic current sources including patent and child current sourcessuch as the current source 471 and current sources 472 are placeddensely in a output current circuit 654 in an area illustrated in FIG.68. The dense placement reduces variations in outputs from the sourcesignal lines 18. As illustrated in FIG. 68, by placing them in theoutput current circuit 654 at the center of the source driver IC(circuit) 14, it becomes easy to distribute current to the left andright of the source driver IC (circuit) 14 from the current source 471and current sources 472, resulting in reduced output variations betweenthe left and right sides (it is all right to place them in a referencecurrent generator circuit or controller instead of the current outputcircuit. That is, 654 is an area where an output circuit is not formed).

However, it is not always necessary to place them in the output currentcircuit 654 at the center They may be placed at an end or both ends ofthe IC chip. Also, they may be formed or placed in parallel with theoutput current circuit 654.

It is not desirable to form a controller or output current circuit 654in the center of the IC chip 14 because they are liable to be affectedby Vt distribution of the unit transistors 484 in the IC chip 14 (the Vtof an wafer is distributed evenly in the wafer).

In the circuit configuration in FIG. 52, transistors 473 a andtransistors 473 b are connected in a one-to-one relationship. In FIG. 51again, transistors 472 a and transistors 472 b are connected in aone-to-one relationship.

However, if transistors are connected in a one-to-one relationship withother transistors, any variation in the characteristics (Vt, etc.) ofcharacteristics of a transistor will result in variations in the outputof the corresponding transistor connected to it.

To solve this problem, an example with an appropriate configuration isshown in FIG. 58. In the configuration shown in FIG. 58, transmissiontransistor groups 521 b (521 b 1, 521 b 2, and 521 b 3) each of whichconsists of four transistors 473 a and transmission transistor groups521 c (521 c 1, 521 c 2, and 521 c 3) each of which consists of fourtransistors 473 b are connected with each other. Although it has beenstated that each of the transistor groups 521 b and 521 c consist offour transistors 473, this is not restrictive and may consist of lessthan four or more than four transistors. That is, a reference current Ibflowing through the transistors 473 a is output from a plurality oftransistors 473 which form a current mirror circuit together with thetransistors 473 a and the output current is received by a plurality oftransistors 473 b.

Preferably, the plurality of transistors 473 a and plurality oftransistors 473 b are approximately equal in size and equal in number.Preferably, the unit transistors 484 (63 in number in the case of 64gradations as in FIG. 48) each of which produces one output and thetransistors 473 b which compose a current mirror together with the unittransistors 484 are also approximately equal in size and equal innumber. Specifically, the difference in size between the unittransistors 484 and transistors 473 b are preferably within ±25%. Theabove configuration makes it possible to set a current mirror ratioaccurately and reduce variations in output current. Incidentally, thearea of a transistor is given by the product of the channel length L andchannel width W of the transistor.

Preferably, the current flowing through the transistors 472 b is equalto or more than five times a current Ic1 passed through the transistors473 b. This will stabilize the gate potential of the transistors 473 aand suppress transient phenomena caused by output current.

Although it has been stated that the transmission transistor group 521 b1 and transmission transistor group 521 b 2 are placed adjacent to eachother and that each of them consists of four transistors 473 a placednext to one another, this is not restrictive. For example, thetransistors 473 a of the transmission transistor group 521 b 1 and thetransistors 473 a of the transmission transistor group 521 b 2 may beplaced or formed alternately. This will reduce variations in the outputcurrent (programming current) of each terminal.

The use of multiple transistors for current-based delivery makes itpossible to reduce variations in output current of the transistor groupas a whole and further reduce variations in the output current(programming current) of each terminal.

The total formation area of the transistors 473 composing a transmissiontransistor group 521 is an important item. Basically, the larger thetotal formation area of the transistors 473, the smaller the variationsin output current (programming current flowing in from the source signalline 18). That is, the larger the formation area of the transmissiontransistor group 521 (the total formation area of the transistors 473),the smaller the variations. However, a larger formation area of thetransistors 473 increases a chip area, increasing the price of the ICchip 14.

Incidentally, the formation area of a transmission transistor group 521is the sum total of the formation areas of the transistors 473 composingthe transmission transistor group 521. The area of a transistor is theproduct of the channel length Land channel width W of the transistor.Thus, if a transistor group 521 consists of ten transistors 473 whosechannel length L is 10 μm and channel width W is 5 μm, the formationarea Tm (square μm) of the transmission transistor group 521 is 10 μm×5μm×10=500 (square μm).

The formation area of the transmission transistor group 521 should bedetermined in such a way as to maintain a certain relationship with theunit transistors 484. Also, the transmission transistor group 521 a andtransmission transistor group 521 b should maintain a certainrelationship.

Now, description will be given of the relationship between the formationarea of the transmission transistor group 521 and the unit transistors484. As also illustrated in FIG. 50, a plurality of unit transistors 484are connected per one transistor 473 b. In the case of 64 gradations, 63unit transistors 484 correspond to one transistor 473 b (configurationin FIG. 48). If the channel length L of the unit transistor 473 is 10 μmand channel width W of the unit transistor 473 is 10 μm, the formationarea Ts (square μm) of the unit transistor group (63 unit transistors484, in this example) is 10 μm×10 μm×63=6300 square μm.

The transistor 473 b in FIG. 48 and transmission transistor groups 521 cin FIG. 58 are relevant here. The formation area Ts of the unittransistor group and formation area Tm of the transmission transistorgroup 521 c have the following relationship:1/4≦Tm/Ts≦6

More preferably, the formation area Ts of the unit transistor group andformation area Tm of the transmission transistor group 521 c have thefollowing relationship:1/2≦Tm/Ts≦4

By satisfying the above relationship, it is possible to reducevariations in the output current (programming current) of each terminal.

Also, the formation area Tmm of the transmission transistor group 521 band formation area Tms of the transmission transistor group 521 c havethe following relationship:1/2≦Tmm/Tms≦8

More preferably, the formation area Ts of the unit transistor group andformation area Tm of the transmission transistor group 521 c have thefollowing relationship:1≦Tm/Ts≦4

By satisfying the above relationship, it is possible to reducevariations in the output current (programming current) of each terminal.

Suppose output current from the transistor group 521 b 1 is Ic1, outputcurrent from the transistor group 521 b 2 is Ic2, and output currentfrom the transistor group 521 b 3 is Ic3. Then, the output currents Ic1,Ic2, and Ic3 must coincide. According to the present invention, sinceeach transistor group 521 consists of multiple transistors 473, even ifindividual transistors 473 have variations, there is no variation in theoutput current Ic of the transistor group 521 as a whole.

Incidentally, the above example is not limited to three-stage currentmirror connections (multi-stage current mirror connections) shown inFIG. 52. Needless to say, it is also applicable to single-stage currentmirror connections. The example shown in FIG. 52 involves connecting thetransistor groups 521 b (521 b 1, 521 b 2, 521 b 3, . . . ) each ofwhich consists of multiple transistors 473 a with the transistor groups521 c (521 c 1, 521 c 2, 521 c 3, . . . ) each of which consists ofmultiple transistors 473 b. However, the present invention is notlimited to this. It is also possible to connect a single transistor 473a with the transistor groups 521 c (521 c 1, 521 c 2, 521 c 3, . . . )each of which consists of multiple transistors 473 b, or to connect thetransistor groups 521 b (521 b 1, 521 b 2, 521 b 3, . . . ) each ofwhich consists of multiple transistors 473 a with one transistor group473 b.

In FIG. 48, the switch 481 a corresponds to the 0th bit, the switch 481b corresponds to the 1st bit, the switch 481 c corresponds to the 2ndbit, . . . , and the switch 481 f corresponds to the 5th bit. The 0thbit consists of one unit transistor, the 1st bit consists of two unittransistor, the 2nd bit consists of four unit transistor, . . . , andthe 5th bit consists of thirty-two (32) unit transistor. For ease ofexplanation, it is assumed that the source driver circuit 14 is a 6-bitdriver supporting 64-gradation display.

With the configuration of the source driver IC (circuit) 14 according tothe present invention, the 1st bit outputs a twice larger programmingcurrent to the 0th bit, the 2nd bit outputs a twice larger programmingcurrent to the 1st bit, the 3rd bit outputs a twice larger programmingcurrent to the 2nd bit, the 4th bit outputs a twice larger programmingcurrent to the 3rd bit, the 5th bit outputs a twice larger programmingcurrent to the 4th bit. To put it in other words, each bit must be ableto output twice as large programming current as the next lower-orderbit.

The configuration in FIG. 58 reduces variations in the output current ofeach terminal by making a plurality of transistors 473 b receive outputcurrent from a plurality of transistors 473 a. FIG. 60 shows aconfiguration which reduces variations in the output current of eachterminal by supplying reference current from both sides of a transistorgroup. Multiple sources are provided for current Ib. Current Ib1 andcurrent Ib2 have the same current value and the transistor whichgenerates the current Ib1 and the transistor which generates the currentIb2 compose a current mirror circuit as a pair.

Thus, in this configuration, a plurality of transistors (currentgenerating means) are formed, placed, or constructed to generatereference currents which prescribe output currents of the unittransistors 484. More preferably, output currents from the plurality oftransistors are connected to current-receiving circuits such astransistors which compose current mirror circuits and the outputcurrents of the unit transistors 484 are controlled by gate voltagesgenerated by the plurality of transistors. Thus, this configurationcontains a plurality of unit transistors 484 and a plurality oftransistors 473 b which compose current mirror circuits. FIG. 58 shows atransistor group consisting of 63 unit transistors 484 as well as fivetransistors composing current mirror circuits.

Preferably, the gate terminal voltage of the unit transistor 484 is setat 0.52 to 0.68 V (both inclusive) is a silicon IC chip is used. Thisrange can reduce variations in the output current of the unit transistor484. The above items similarly apply to other examples of the presentinvention in FIGS. 163, 164, 165, etc.

In FIG. 60, if the reference current Ib1 and reference current Ib2 aredesigned to be independently adjustable, voltages at point a and point bof a gate terminal 581 can be set freely. The adjustment of thereference currents Ib1 and Ib2 makes it possible to correct any slope ofoutput current caused by difference in the Vt of unit transistorsbetween the left and right sides of the IC chip 14.

Preferably, the currents generated by the transistors composing currentmirror circuits are delivered by a plurality of transistors. Transistorsformed in an IC chip 14 have variations in characteristics. To suppressvariations in transistor characteristics, the size of the transistorscan be increased. However, if transistor size is increased, the currentmirror ratios of the current mirror circuits may deviate. To solve thisproblem, it is advisable to make current- or voltage-based deliveryusing a plurality of transistors. The use of multiple transistorsdecreases overall variations even if there are variations in thecharacteristics of individual transistors. This also improves theaccuracy of current mirror ratios. All in all, the area of the IC chipis reduced as well.

In FIG. 58, the transistor group 521 a and transistor groups 521 bcompose current mirror circuits. The transistor 521 a consists of aplurality of transistors 472 b. On the other hand, each of thetransistor groups 521 b consists of a plurality of transistors 473 a.Similarly, each of the transistor groups 521 c consists of a pluralityof transistors 473 c.

The transistor group 521 b 1, transistor group 521 b 2, transistor group521 b 3, transistor group 521 b 4, and so on are composed of the samenumber of transistors 473 a. Also, the total area of the transistors 473a is (approximately) equal among the transistor groups 521 b (where thetotal area is the W and L sizes of the transistors 473 a in eachtransistor group 521 b multiplied by the number of the transistors 473a) The same applies to the transistor groups 521 c.

Let Sc denote the total area of the transistors 473 b in each transistorgroup 521 c (where the total area is the W and L sizes of thetransistors 473 b in each transistor group 521 c multiplied by thenumber of the transistors 473 b). Also, let Sb dente the total area ofthe transistors 473 a in each transistor group 521 b (where the totalarea is the W and L sizes of the transistors 473 a in each transistorgroup 521 b multiplied by the number of the transistors 473 a). Also,let Sa dente the total area of the transistors 472 b in the transistor521 a (where the total area is the W and L sizes of the transistors 472b in the transistor group 521 a multiplied by the number of thetransistors 472 b). Also, let Sd dente the total area of the unittransistors 484 per output (where the total area is the W and L sizes ofthe unit transistor 484 multiplied by 63).

Preferably, the total area Sc and the total area Sb are approximatelyequal. Also, it is preferably that the transistors 473 a composing eachtransistor group 521 b and the transistors 473 b composing eachtransistor group 521 c are equal in number. However, considering layoutconstraints on the IC chip 14, the transistors 473 a composing eachtransistor group 521 b may be made smaller in number and larger in sizethan the transistors 473 b composing each transistor group 521 c.

An example of the above configuration is shown in FIG. 59. Thetransistor group 521 a consists of a plurality of transistors 472 b. Thetransistor group 521 a and transistors 473 a compose a current mirrorcircuit. The transistors 473 a generates current Ic. One transistor 473a drives a plurality of transistors 473 b in a transistor group 521 c(the current Ic from the single transistor 473 a is shunted to theplurality of transistors 473 b. Generally, the number of transistors 473a corresponds to the number of output circuits. For example, in a QCIF+panel, there are 176 transistors 473 a in each of R, G, and B circuits.

The relationship between the total area Sd and total area Sc iscorrelated with output variations. This correlation is shown in FIG.124. For a variation rate and the like, refer to FIG. 121. The variationrate when total area Sd: total area Sc=2:1 (Sc/Sd=1/2) is taken as 1. Ascan bee seen from FIG. 124, a small Sc/Sd ratio results in a sharpdeterioration in the variation rate. A poor variation rate resultsespecially when Sc/Sd is 1/2 or less. Output variations decrease whenSc/Sd is 1/2 or above. The decrease is gradual. Output variations fallwithin an allowable range when Sc/Sd is around 1/2 or larger. In view ofthe above circumstances, it is preferable that 1/2≦Sc/Sd is satisfied.However, a larger Sc means a larger IC chip. Thus, an upper limit ofSc/Sd=4 should be provided. That is, a relationship 1/2≦Sc/Sd≦4 shouldbe satisfied.

Incidentally, A≧B means that A is equal to or larger than B. A>B meansthat A is larger than B. A≦B means that A is equal to or smaller than B.A<B means that A is smaller than B.

Besides, preferably the total area Sd and total area Sc areapproximately equal. Furthermore, preferably the number of the unittransistors 484 per output and the number of the transistors 473 b ineach transistor group 521 c are equal. That is, in the case of 64gradations, there are 63 unit transistors 484 per output. Thus, thereare 63 transistors 473 b in the transistor group 521 c.

Also, preferably the transistor group 521 a, transistor groups 521 b,and the transistor groups 521 c are composed of unit transistors 484whose W/L ratio is within a factor of four. More preferably, they arecomposed of unit transistors 484 whose W/L ratio is within a factor oftwo. Even more preferably, they are composed of unit transistors 484 ofthe same size. That is, current mirror circuits and the output currentcircuit 654 are composed of transistors of approximately the same size.

The total area Sa should be larger than the total area Sb. Preferably, arelationship 200 Sb≧Sa≧4 Sb is satisfied. Also, the total area Sa of thetransistors 473 a composing all the transistor groups 521 b should beapproximately equal to Sa.

In the configuration shown in FIG. 60 and the like, a transistor ortransistor group is placed at each end of the gate wiring 581. Thus, atotal of two transistors or two transistor groups are placed at bothends of the gate wiring 581. However, the present invention is notlimited to this. As illustrated in FIG. 61, a transistor or transistorgroup may be placed at the center or other location of the gate wiring581. Three transistor groups 521 a are formed in FIG. 61. The presentinvention is characterized in that a plurality of transistors ortransistor groups 521 are formed on the gate wiring 581. The use ofmultiple transistors or transistor groups makes it possible to reducethe impedance of the gate wiring 581, resulting in improved stability.

To further improve the stability, it is preferable to form or place acapacitor 661 on the gate wiring 581 as illustrated in FIG. 62.Alternatively, the capacitor 661 may be formed in the IC chip 14 orsource driver circuit 14 or placed or mounted outside the chip as anexternal capacitor of the source driver IC 14. When mounting thecapacitor 661 externally, a capacitor connection terminal is placed onan IC chip terminal.

The above example is configured to pass a reference current, copy thereference current using a current mirror circuit, and transmit thereference current to the unit transistor 484 in the final stage. Whenthe image display is black display (complete black raster), current doesnot flow through any unit transistor 484 because every switch is open.Thus, 0 (A) current flows through the source signal line 18, consumingno power.

However, even during black raster display, reference currents flow.Examples include the current Ib and Ic in FIG. 63. They become reactivecurrents. Reference currents flow efficiently if configured to flowduring current programming. Thus, the flow of reference current islimited during vertical and horizontal blanking periods of images. Also,the flow of reference current is limited during wait periods.

To prevent reference current from flowing, a sleep switch 631 can beopened as shown in FIG. 63. The sleep switch 631 is an analog switch.The analog switch is formed in the source driver circuit or sourcedriver IC 14. Of course, the sleep switch 631 may be placed outside thesource driver IC 14 and controlled.

When the sleep switch 631 is turned off, the reference current Ib stopsflowing. Consequently, current does not flow through the transistors 473a in a transistor group 521 a 1, and the reference current Ic is alsoreduced to 0 A. Thus, current does not flow through the transistors 473b in a transistor group 521 c either. This improves power efficiency.

FIG. 64 is a timing chart. A blanking signal is generated in sync with ahorizontal synchronization signal HD. The period when the blankingsignal is high corresponds to a blanking period. When the blankingsignal is low, a video signal is being applied. The sleep switch 631 isoff (open) when the blanking signal is low, and on when the signal ishigh.

During a blanking period A when the sleep switch 631 is off, referencecurrent does not flow. During a period D when the sleep switch 631 ison, the reference current flows.

Incidentally, on/off control of the sleep switch 631 may be performedaccording to image data. For example, when all image data in a pixel rowis black image data (for a period of 1 H, the programming currentsoutputted to all source signal lines 18 are 0), the sleep switch 631 isturned off to stop reference currents (Ic, Ib, etc.) from flowing. Also,asleep switch may be formed or placed for each source signal line and besubjected to on/off control. For example, when an odd-numbered sourcesignal line 18 is in black display mode (vertical black stripe display),the corresponding sleep switch is turned off.

FIGS. 52 and 77 are block diagrams of source driver circuits (ICs) 14with a configuration of a current mirror with multi-stage connections.The present invention is not limited to multi-stage connectionconfiguration such as the one shown in FIG. 52. It is also applicable toa source driver circuit with single stage connections. FIGS. 166 to 172are block diagrams of source driver circuits (ICs) with a single stageconnection.

With a source driver circuit with single stage connections, inparticular, when images are displayed on a display panel, currentapplied to source signal lines 18 causes fluctuations in source signalline potential, which in turn cause the gate wiring 581 of the sourcedriver IC 14 to swing. The swing is influenced by the power supplyvoltage of the source driver IC 14 because the power supply voltageswings to a maximum voltage. FIG. 163 shows a ratio of potentialfluctuations of the gate wiring based on the value obtained when thepower supply voltage of the source driver IC 14 is 1.8 V. Thefluctuation ratio increases with increases in the power supply voltageof the source driver IC 14. An allowable range of fluctuation ratio isapproximately 3. A higher fluctuation ratio will cause horizontalcross-talk. The fluctuation ratio with respect to the power supplyvoltage tends to increase when the power supply voltage of the IC is 10to 12 V or higher. Thus, the power supply voltage of the source driverIC 14 should be 12 V or less.

On the other hand, in order for a driver transistor 11 a switch fromwhite-display current to black-display current, it is necessary to makea certain amplitude change to the potential of the source signal line18. The required range of amplitude change is 2.5 V or more. It is lowerthan the power supply voltage because the output voltage of the sourcesignal line 18 cannot exceed the power supply voltage.

Thus, the power supply voltage of the source driver IC 14 should be from2.5 V to 12 V (both inclusive). The use of this range makes it possibleto keep fluctuations in the gate wiring 581 within a stipulated range,eliminate horizontal cross-talk, and thus achieve proper image display.

Wiring resistance of the gate wiring 581 also presents a problem. InFIG. 167, the wiring resistance (Ω) of the gate wiring 581 is theresistance of the wiring throughout its length from transistor 473 b 1to transistor 473 b 2 or the resistance of the gate wiring throughoutits length. The magnitude of a transient phenomenon of the gate wiring581 depends on one horizontal scanning period (1 H) as well because theshorter the period of 1 H, the larger the impact of the transientphenomenon. A larger wiring resistance (Ω) makes a transient phenomenoneasier to occur. This phenomenon poses a problem especially for theconfigurations of single-stage current-mirror connections shown in FIGS.166 to 172, in which the gate wiring 581 is long and connected with alarge number of unit transistors 484.

FIG. 164 is a graph in which the horizontal axis represents the product(R·T) of wiring resistance (Ω) of the gate wiring 581 and 1-H period T(sec) while the vertical axis represents a fluctuation ratio. Thefluctuation ratio is taken as 1 when R·T=100. As can be seen from FIG.212, fluctuation ratio tends to grow larger when R·T is 5 or less.Fluctuation ratio also tends to grow larger when R·T is 1000 or more.Thus, it is preferable that R·T is from 5 to 100 (both inclusive).

In FIG. 167, the transistor 472 b and two transistors 473 a compose acurrent mirror circuit. The transistor 473 a 1 and transistor 473 a 2are of the same size. Thus, current Ic passed by the transistor 473 a 1and current Ic passed by the transistor 473 a 2 are identical.

In FIG. 167, the transistor groups 521 c consisting of unit transistors484 compose current mirror circuits together with the transistor 473 b 1and transistor 473 b 2. There are variations in the output current ofthe transistor groups 521 c. However, transistor groups 521 whichcompose a current mirror circuit in close vicinity to each other havetheir output current controlled accurately. The transistor 473 b 1 andtransistor group 521 c 1 compose a current mirror circuit in closevicinity to each. Also, The transistor 473 b 2 and transistor group 521cn compose a current mirror circuit in close vicinity to each. If thecurrent flowing through the transistor 473 b 1 and the current flowingthrough the transistor 473 b 2 are equal, the output current of thetransistor group 521 c 1 and the output current of the transistor group521 cn are equal. If the current is generated in each IC chipaccurately, the output currents of the transistor groups 521 c at bothends of the output stage are equal in any IC chip. Thus, even if ICchips are cascaded, seams between ICs can be made inconspicuous.

As is the case with FIG. 62, a plurality of transistors 473 b may beprovided to form a transistor group 521 b 1 and transistor 521 b 2.Also, a plurality of transistors 473 a may be provided to form atransistor group 521 a as in FIG. 62.

Although it has been stated that the transistor 472 b current isspecified by the resistance R1, this is not restrictive. Electronicregulators 451 a and 451 b may be used as shown in FIG. 170. In theconfiguration shown in FIG. 170, the electronic regulators 451 a and 451b can be operated independently. Thus, the values of the currentsflowing through the transistors 472 a 1 and 472 a 2 can be changed. Thismakes it possible to adjust the slopes of the output currents in outputstages 521 c on the left and right sides of the chip. Incidentally, itis also possible to provide only one electronic regulator 451 as shownin FIG. 171 and use it to control two operational amplifiers 722. Thesleep switch 631 has been described with reference to FIG. 63. Needlessto say, a sleep switch may be placed or formed similarly as shown inFIG. 172.

The single-stage current-mirror configurations in FIGS. 166 to 172contain very large numbers of unit transistors 484. Thus, an additionaldescription will be given of the output stage of the source drivercircuit 14. Incidentally, for ease of explanation, FIGS. 168 and 169will be taken as an example. However, since the description concerns thenumber and total area of transistors 473 b as well as the number andtotal area of unit transistors 484, it goes without saying that thedescription applies to other examples as well.

FIGS. 168 and 169, let Sb denote the total area of the transistors 473 bin each transistor group 521 b (where the total area is the W and Lsizes of the transistors 473 b in each transistor group 521 b multipliedby the number of the transistors 473 b). Incidentally, if transistorgroups 521 b are installed on the left and right of the gate wiring 581as in FIGS. 168 and 169, the area is doubled. If there are twotransistors, Sb equals the area of the transistor 473 b multiplied by 2.If the transistor group 521 b consists of a single transistor 473 b,needless to say, Sb equals the size of the one transistor 473 b.

Also, let Sc denote the total area of the unit transistors 484 in eachtransistor group 521 c (where the total area is the W and L sizes of thetransistors 484 in each transistor group 521 c multiplied by the numberof the transistors 484). It is assumed that the number of the transistorgroups 521 c is n. In the case of a QCIF+ panel, n is 176 (a referencecurrent circuit is formed for each of R, G, and B).

In FIG. 165, the horizontal axis represents Sc×n/Sb and the verticalaxis represents a fluctuation ratio. The fluctuation ratio in the worstcase is taken as 1. As illustrated in FIG. 165, the fluctuation ratiodeteriorates with increases in Sc×n/Sb. A large value of Sc×n/Sb meansthat the total area of the unit transistors 484 in the transistor groups521 c is larger than the total area of the transistors 473 b in thetransistor groups 521 b when the number n of output terminals isconstant. In that case, the fluctuation ratio is unfavorable.

A small value of Sc×n/Sb means that the total area of the unittransistors 484 in the transistor groups 521 c is smaller than the totalarea of the transistors 473 b in the transistor groups 521 b when thenumber n of output terminals is constant. In that case, the fluctuationratio is small.

An allowable range of fluctuations corresponds to a value of Sc×n/Sb of50 or less. When Sc×n/Sb is 50 or less, the fluctuation ratio fallswithin the allowable range and potential fluctuations of the gate wiring581 is extremely small. This makes it possible to eliminate horizontalcross-talk, keep output variations within an allowable range, and thusachieve proper image display. It is true that the fluctuation ratiofalls within the allowable range when Sc×n/Sb is 50 or less. However,decreasing Sc×n/Sb to 5 or less has almost no effect. On the contrary,Sb becomes large, increasing the chip area of the IC 14. Thus,preferably Sc×n/Sb to 5 should be from 5 to 50 (both inclusive).

If P-channel transistors are used as the transistors 11 of pixels 16,programming current flows in the direction from the pixels 16 to thesource signal lines 18. Thus, N-channel transistors should be used asthe unit transistors 484 of the source driver circuits 14 (see FIGS. 48and 57). That is, the source driver circuits 14 should be configured insuch a way as to draw the programming current Iw.

Thus, if the driver transistors 11 a of the pixels 16 (in the case ofFIG. 1) are P-channel transistors, the unit transistors 484 of thesource driver circuits 14 must be N-channel transistors to ensure thatthe source driver circuits 14 will draw the programming current Iw. Inorder to form a source driver circuit 14 on an array board 71, it isnecessary to use both mask (process) for N-channel transistors and mask(process) for P-channel transistors. Conceptually speaking, in thedisplay panel (display apparatus) of the present invention, P-channeltransistors are used for the pixels 16 and gate driver circuits 12 whileN-channel transistors are used as the transistors of drawing currentsources of the source drivers.

Thus, P-channel transistors are used as the transistors 11 of pixels 16and for the gate driver circuits 12. This makes it possible to reducethe costs of the array boards 71. However, in the source driver circuits14, unit transistors 484 must be N-channel transistors. Thus, the sourcedriver circuits 14 can not be formed directly on array boards 71. Thus,the source driver circuits 14 are made of silicon chips and the likeseparately and mounted on the array board 71. In short, the presentinvention is configured to mount source driver circuits 14 (means ofoutputting programming current as video signals) externally.

Incidentally, although it has been stated that the source drivercircuits 14 are made of silicon chips, this is not restrictive. Forexample, a large number of source driver circuits may be formed on aglass substrate simultaneously using low-temperature polysilicontechnology or the like, cut off into chips, and mounted on an arrayboard 71. Incidentally, although it has been stated that source drivercircuits are mounted on an array board 71, this is not restrictive. Anyform may be adopted as long as the output terminals 521 of the sourcedriver circuits 14 are connected to the source signal lines 18 of thearray board 71. For example, the source driver circuits 14 may beconnected to the source signal lines 18 using TAB technology. By formingsource driver circuits 14 on a silicon chip separately, it is possibleto reduce variations in output current and achieve proper image displayas well as to reduce costs.

The configuration in which P-channel transistors are used as selectiontransistors of pixels 16 and for gate driver circuits is not limited toorganic EL or other self-luminous devices (display panels or displayapparatus). For example, it is also applicable to liquid crystal displaypanels and FEDs (field emission displays).

If the switching transistors 11 b and 11 c of a pixel 16 are P-channeltransistors, the pixel 16 becomes selected at Vgh, and becomesdeselected at Vgl. As described earlier, when the gate signal line 17 achanges from Vgl (on) to Vgh (off), voltage penetrates (penetrationvoltage). If the driver transistor 11 a of the pixel 16 is a P-channeltransistor, the penetration voltage restricts the flow of currentthrough the transistor 11 a in black display mode. This makes itpossible to achieve a proper black display. The problem with thecurrent-driven system is that it is difficult to achieve a blackdisplay.

According to the present invention, which uses P-channel transistors forthe gate driver circuits 12, the turn-on voltage corresponds to Vgh.Thus, the gate driver circuits 12 match well with the pixels 16constructed from P-channel transistors. Also, to improve black display,it is important that the programming current Iw flows from the anodevoltage Vdd to the unit transistors 484 of the source driver circuits 14via the driver transistors 11 a and source signal lines 18, as is thecase with the pixel 16 configuration shown in FIGS. 1, 2, 32, 113, and116. Thus, a good synergistic effect can be produced if P-channeltransistors are used for the gate driver circuits 12 and pixels 16, thesource driver circuits 14 are mounted on the substrate, and N-channeltransistors are used as the unit transistors 484 of the source drivercircuits 14. Besides, unit transistors 484 constituted of N-channeltransistors have smaller variations in output current than unittransistors 484 constituted of P-channel transistors. N-channel unittransistors 484 have 1/1.5 to 1/2 as large variations in output currentas P-channel unit transistors 484 when they have the same area (W·L).For this reason, it is preferable that N-channel transistors are used asthe unit transistors 484 of the source driver circuits 14.

The same applies to FIG. 42(b). FIG. 42(b) shows a configuration inwhich a programming current Iw flows from an anode voltage Vdd to theunit transistors 484 of a source driver circuit 14 via a programmingtransistor 11 a and source signal line 18 rather than a configuration inwhich current flows into the unit transistors 484 of a source drivercircuit 14 via a driver transistor 11 b. Thus, as in the case of FIG. 1,a good synergistic effect can be produced if P-channel transistors areused for the gate driver circuits 12 and pixels 16, the source drivercircuits 14 are mounted on the substrate, and N-channel transistors areused as the unit transistors 484 of the source driver circuits 14.

According to the present invention, the driver transistors 11 a of thepixels 16 are P-channel transistors and the switching transistors 11 band 11 c are P-channel transistors. Also, the unit transistors 484 inthe output stages of the source driver circuits 14 are N-channeltransistors. Besides, preferably P-channel transistors are used for thegate driver circuits 12.

Needless to say, a configuration in which P-channel and N-channeltransistors are interchanged also works well. Specifically, the drivertransistors 11 a of the pixels 16 are N-channel transistors and theswitching transistors 11 b and 11 c are N-channel transistors. Also, theunit transistors 484 in the output stages of the source driver circuits14 are P-channel transistors. Besides, preferably N-channel transistorsare used for the gate driver circuits 12. This configuration alsobelongs to the present invention.

Now, reference current circuits according to the present invention willbe described below. As illustrated in FIG. 68, a reference currentcircuit 691 is formed (placed) for each of R, G, and B. Also, thereference current circuits 691R, 691G, and 691B are placed close to eachother.

A regulator (electronic regulator) 491R for reference current adjustmentis placed in a reference current circuit 654R for R, a regulator(electronic regulator) 491G for reference current adjustment is placedin a reference current circuit 654G for G, and a regulator (electronicregulator) 491B for reference current adjustment is placed in areference current circuit 654B for B.

Preferably, the regulators 491 should be capable of accommodatingtemperature changes to compensate for temperature characteristics of theEL element 15. Also, as illustrated in FIG. 69, the reference currentcircuits 691 are controlled by current control circuits 692. Bycontrolling (adjusting) the reference current, it is possible to varyunit current outputted from the unit transistors 484.

Output pads 681 are formed or placed on the output terminals of the ICchip and connected with the source signal lines 18 of the display panel.A bump is formed on the output pads 681 by a plating technique or ballbonding technique. The bump should be 10 to 40 μm high (both inclusive).

The bumps and the source signal lines 18 are connected electrically viaa conductive bonding layer (not shown). The conductive bonding layer ismade of a epoxy or phenolic base resin mixed with flakes of silver (Ag),gold (Au), nickel (Ni), carbon (C), tin oxide (SnO2), and the like, ormade of a ultraviolet curing resin. The conductive bonding layer isformed on the bump by a transfer or other technique. Incidentally, thetechniques for connecting the bumps or output pads 681 with the sourcesignal lines 18 are not limited to those described above. Besides, afilm carrier technique may be used instead of mounting the IC 14 on thearray board. Also, polyimide films may be used for connection with thesource signal lines 18.

The present invention, which provides separate reference currentcircuits 691 for R, G, and B, makes it possible to adjust emissioncharacteristics and temperature characteristics separately for R, G, andB, and thereby obtain an optimum white balance (see FIG. 70).

Next, a precharge circuit will be described. As described earlier, inthe case of current driving, only a small current is written into pixelsduring black display. Consequently, if the source signal lines 18 or thelike have parasitic capacitance, current cannot be written into thepixels 16 sufficiently during one horizontal scanning period (1 H).Generally, in current-driven light-emitting elements, black-levelcurrent is as weak as a few nA, and thus it is difficult to driveparasitic capacitance (load capacitance of wiring) which is assumed tomeasure tens of pF using the signal value of the black-level current. Tosolve this problem, it is useful to equalize the black-level current inthe pixel transistors 11 a (basically, the transistors 11 a are off)with the potential level of the source signal lines 18 by applying aprecharge voltage before writing image data into the source signal lines18. In order to form (create) the precharge voltage, it is useful tooutput the black level at a constant voltage by decoding higher orderbits of image data.

FIG. 65 shows an example of a current-output type source driver IC(circuit) 14 equipped with a precharge function according to the presentinvention. FIG. 65 shows a case in which the precharge function isprovided in the output stage of a 6-bit constant-current output circuit.In FIG. 65, when the higher order three bits D3, D4, and D5 in imagedata D0 to D5 are all zero, a precharge control signal causes a NORcircuit 652 to decode the image signal, causes an AND circuit 653 to ANDthe results with an output from a counter circuit 651 of a dot clockCLK, and thereby causes a black level voltage Vp to be output for afixed period, where the dot clock CLK is equipped with a reset functionbased on a horizontal synchronization signal HD. In the other cases, anoutput current from a current output stage 654 (specifically,configurations in FIGS. 48, 56, 57, etc.) is applied to the sourcesignal lines 18 (programming current Iw is drawn from the source signallines 18). When the image data is composed of the 0th to 7th gradationsclose to the black level, by writing a voltage which corresponds to theblack level for a fixed period at the beginning of a horizontal period,the above configuration reduces the burden of current driving and makesup for insufficient writing. Incidentally, it is assumed that the 0thgradation corresponds to a completely black display while the 63rdgradation corresponds to a completely white display (in the case of64-gradation display).

In FIG. 65, any precharge voltage supplied is applied to point B oninternal wiring 483. Thus, it is applied to the current output stage 654as well. However, since the current output stage 654 constitutes aconstant-current circuit, it has high impedance. Thus, even if theprecharge voltage is applied to the current output stage 654, there isno problem with circuit operation. Incidentally, to prevent theprecharge voltage from being applied to the current output stage 654, aswitch 655 can be installed by cutting the circuit at point A in FIG. 65(see FIG. 66). This switch should be made to work in coordination with aprecharge switch 481 a such that it will be off when the prechargeswitch 481 a is on.

Although precharging may be performed over the entire range ofgradations, preferably precharging should be limited to a black displayregion. Specifically, precharging is performed by selecting gradationsin a black region (low brightness, region, in which only a small (weak)current flows in the case of current driving) from write image data(hereinafter, this type of precharging will be referred to as selectiveprecharging). If precharging is performed over the entire range ofgradations, brightness lowers (a target brightness is not reached) in awhite display region. Also, vertical streaks may be displayed in somecases.

Preferably, selective precharging is performed for 1/8 of all thegradations beginning with the 0th gradation (e.g., in the case of 64gradations, image data is written after precharging for the 0th to 7thgradations). More preferably, selective precharging is performed for1/16 of all the gradations beginning with the 0th gradation (e.g., inthe case of 64 gradations, image data is written after precharging forthe 0th to 3rd gradations).

A method which performs precharging by detecting only the 0th gradationis also effective in enhancing contrast, especially in black display. Itachieves an extremely good black display. The method of performingprecharging by extracting only the 0th gradation causes little harm toimage display. Thus, it is most preferable to adopt this method as aprecharging technique.

Incidentally, it is also useful to vary the precharge voltage andgradation range among R, G, and B because emission start voltage andemission brightness of EL elements 15 vary among R, G, and B. Forexample, selective precharging is performed for 1/8 of all thegradations beginning with the 0th gradation (e.g., in the case of 64gradations, image data is written after precharging for the 01th to 7thgradations) in the case of R. In the case of other colors (G and B),selective precharging is performed for 1/16 of all the gradationsbeginning with the 0th gradation (e.g., in the case of 64 gradations,image data is written after precharging for the 0th to 3rd gradations).Regarding the precharge voltage, if 7 V is written into the sourcesignal lines 18 for R, 7.5 V is written into the source signal lines 18for the other colors (G and B). Optimum precharge voltage often varieswith the production lot of the EL display panel. Thus, preferablyprecharge voltage can be adjustable with an external regulator. Such aregulator circuit can be implemented easily using an electronicregulator.

Incidentally, it is preferable that the precharge voltage is not higherthan the anode voltage Vdd minus 0.5 V and within the anode voltage Vddminus 2.5 V in FIG. 1.

Even with methods which perform precharging only for the 0th gradation,it is useful to perform precharging selecting one or two colors fromamong R, G, and B. This will cause less harm to image display. It isalso useful to perform precharging when the screen brightness is below apredetermined brightness or above a predetermined brightness. Inparticular, when the brightness of the screen 50 is low, black displayis difficult. Precharge driving at low contrast such as 0-gradationprecharging will improve perceived contrast of images.

It is preferable to provide several modes which can be switched by acommand: including a 0th mode in which no precharging is performed,first mode in which precharging is performed only for the 0th gradation,second mode in which precharging is performed in the range of the 0th to3rd gradations, third mode in which precharging is performed in therange of the 0th to 7th gradations, and fourth mode in which prechargingis performed in the entire range of gradations. These modes can beimplemented easily by constructing (designing) a logic circuit in thesource driver circuit (IC) 14.

FIG. 66 is a diagram showing a concrete configuration of a selectiveprecharging circuit. Reference character PV denotes an input terminal ofprecharge voltage. Separate precharge voltages are set for R, G, and Bby external inputs or by an electronic regulator circuits. Incidentally,although it has been stated that separate precharge voltages are set forR, G, and B, this is not restrictive. Precharge voltages may be commonto R, G, and B because they are correlated with the Vt of the drivertransistors 11 a of the pixels 16, which do not differ among R, G, andB. If the W/L ratio and the like of the driver transistors 11 a of thepixels 16 are varied (designed differently) among R, G, and B,preferably the precharge voltage is adjusted to the different designs.For example, a larger channel length L of the driver transistor 11 alowers diode characteristics of the transistor 11 a and increases thesource-drain (SD) voltage. Thus, the precharge voltage should be setlower than the source potential (Vdd).

The precharge voltage PV is fed to an analog switch 561. To reduceon-resistance, the W (channel width) of the analog switch 561 should be10 μm or above. However, it is set to 100 μm or below because too largeW will increase parasitic capacitance as well. More preferably, thechannel width W should be 15 to 60 μm (both inclusive).

Incidentally, although selective precharging may be performed for fixedgradations such as only the 0th gradation or a range of the 0th to 7thgradations, it may be performed automatically in any low gradationregion specified (gradation 0 to gradation R1 or gradation R1−1 in FIG.79). Specifically, if a low gradation region ranging from gradation 0 togradation R1 is specified, selective precharging will be performedautomatically in this range, and if a low gradation region ranging fromgradation 0 to gradation R2 is specified, selective precharging will beperformed automatically in this range.

The switch 481 a is turned on and off according to applied signals. Whenthe switch 481 a is turned on, the precharge voltage PV is applied tothe source signal line 18. Incidentally, the duration of application ofthe precharge voltage PV is set by a counter (not shown) formedseparately. The counter is configurable by commands. Preferably, theapplication duration of the precharge voltage is from 1/100 to 1/5 ofone horizontal scanning period (1 H) both inclusive. For example, if 1 His 100 μsec, the application duration should be from 1 μsec to 20 sec(from 1/100 to 1/5 of 1 H) both inclusive. More preferably, it should befrom 2 μsec to 10 μsec (from 2/100 to 1/10 of 1 H) both inclusive.

FIG. 67 shows a variation of FIG. 65 or 66. It shows a precharge circuitwhich determines whether to perform precharging according to input imagedata and controls precharging. For example, the precharge circuit canmake a setting so as to perform precharging when image data containsonly the 0th gradation, perform precharging when image data containsonly the 0th and 1st gradations, or always perform precharging when the0th gradation occurs and perform precharging when the 1st gradationoccurs consecutively for a predetermined number of times.

FIG. 67 shows an example of a current-output type source driver IC(circuit) 14 equipped with a precharge function according to the presentinvention. FIG. 67 shows a case in which the precharge function isprovided in the output stage of a 6-bit constant-current output circuit.In FIG. 67, a coincidence circuit 671 performs decoding according toimage data D0 to D5 and determines whether to perform precharging usinginput in an REN terminal equipped with a reset function based on ahorizontal synchronization signal HD and input in a dot clock CLKterminal. The coincidence circuit 671 has a memory and retains resultsof precharging in relation to image data for a few Hs or a few fields(frames). Also, it has capabilities to control precharging bydetermining whether to perform precharging, based on the retained data.For example, the coincidence circuit 671 can make settings so as toalways perform precharging when the 0th gradation occurs and performprecharging when the 1st gradation occurs consecutively for 6 H (sixhorizontal scanning periods) or more. Also it can make settings so as toalways perform precharging when the 0th or 1st gradation occurs andperform precharging when the 2nd gradation occurs consecutively for 3 Fs(three frame periods) or more.

The output from the coincidence circuit 671 and output from the countercircuit 651 are ANDed by the AND circuit 653, and consequently a blacklevel voltage Vp is output for a predetermined period. In another case,the output current from the current output stage 654 described withreference to FIG. 52 and the like is applied to the source signal lines18 (programming current Iw is drawn from the source signal lines 18).The other configuration is the same as or similar to those shown inFIGS. 65, 66, and the like, and thus description thereof will beomitted. Incidentally, although the precharge voltage is applied topoint A in Figure A, needless to say, it may be applied to point B (seealso FIG. 66).

Good results can also be obtained if the duration of application of theprecharge voltage PV is varied using the image data applied to thesource signal lines 18. For example, the application duration may beincreased for the 0th gradation of completely black display, and madeshorter for the 4th gradation. Also, good results can be obtained if theapplication duration is specified taking into consideration thedifference between image data and image data to be applied 1 H later.For example, when writing a current into the source signal lines to putthe pixels in black display mode 1 H after writing a current into sourcesignal lines to put the pixels in white display mode, the precharge timeshould be increased. This is because a weak current is used for blackdisplay. Conversely, when writing a current into the source signal linesto put the pixels in white display mode 1 H after writing a current intosource signal lines to put the pixels in black display mode, theprecharge time should be decreased or precharging should be stopped.This is because a large current is used for white display.

It is also useful to vary the precharge voltage depending on the imagedata to be applied. This is because a weak current is used for blackdisplay and a large current is used for white display. Thus, it isuseful to raise the precharge voltage (compared to Vdd. When P-channeltransistors are used as pixel transistor 11 a) in a low gradation regionand lower the precharge voltage (when P-channel transistors are used aspixel transistor 11 a) in a high gradation region.

For ease of understanding, description will be given below mainly withreference to FIG. 66. Needless to say, however, the items describedbelow also apply to precharge circuits shown FIGS. 65 and 67.

When a programming current open terminal (PO terminal) is “0,” theswitch 655 is off, disconnecting an IL terminal and IH terminal from thesource signal line 18 (an Iout terminal is connected with the sourcesignal line 18). Thus, the programming current Iw does not flow to thesource signal line 18. When the programming current Iw is applied to thesource signal line, the PO terminal is “1,” keeping the switch 655 on topass the programming current Iw to the source signal line 18.

“0” is applied to the PO terminal to open the switch 655 when no pixelrow in the display area is selected. The unit transistor 484 constantlydraws current from the source signal line 18 based on input data (D0 toD5). This current flows into the source signal line 18 from the Vddterminal of the selected pixel 16 via the transistor 11 a. Thus, when nopixel row is selected, there is no path for current to flow from thepixel 16 to the source signal line 18. A period when no pixel row isselected occurs from the time when an arbitrary pixel row is selected tothe time when the next pixel row is selected. Incidentally, the periodduring which no pixel (pixel row) is selected and there is no path forcurrent to flow into (flow out into) the source signal line 18 isreferred to as total non-selection period.

In this state, if the output terminal 681 is connected to the sourcesignal line 18, current flows to activated unit transistors 484(actually, what is activated are switches 481 controlled by data fromthe D0 to D5 terminals). Consequently, electric charges are dischargedfrom the parasitic capacitance of the source signal line 18, loweringthe potential of the source signal line 18 sharply. Then, it takes timefor the current normally written into the source signal line 18 torestore the potential of the source signal line 18.

To solve this problem, the present invention applies “0” to the POterminal during the total non-selection period to turn off the switch655 in FIG. 66, and thereby disconnect the output terminal 681 from thesource signal line 18. Consequently, no current flows from the sourcesignal line 18 into the unit transistors 484, and thus the potential ofthe source signal line 18 does not change during the total non-selectionperiod. In this way, by controlling the PO terminal during the totalnon-selection period and disconnecting current sources from the sourcesignal line 18, it is possible to write current properly.

It is useful to add a (proper precharging) capability to stopprecharging when a white display area (area with a certain brightness)(white area) and a black display area (area with brightness below apredetermined level) (black area) coexist in the screen and the ratio ofthe white area to the black area falls within a certain range becausevertical streaks appear in this range. Conversely, precharging may bedone in this range because images may act as noise when they move.Proper precharging can be implemented easily by counting (calculating)pixel data which correspond to the white area and black area using anarithmetic circuit.

It is also useful to vary precharge control among R, G, and B becauseemission start voltage and emission brightness of EL elements 15 varyamong R, G, and B. For example, a possible method involves stopping orstarting precharging for R when the ratio of a white area with apredetermined brightness to a black area with a predetermined brightnessis 1 to 20 or above and stopping or starting precharging for G and Bwhen the ratio of a white area with a predetermined brightness to ablack area with a predetermined brightness is 1 to 16 or above. It hasbeen shown experimentally and analytically that in an organic EL panel,preferably precharging should be stopped or started when the ratio of awhite area with a predetermined brightness to a black area with apredetermined brightness is 1 to 100 or above (i.e., the black area isat least 100 times larger than the white area). More preferably,precharging should be stopped or started when the ratio of a white areawith a predetermined brightness to a black area with a predeterminedbrightness is 1 to 200 or above (i.e., the black area is at least 200times larger than the white area).

As shown in FIG. 1, when the driver transistor 11 a of the pixel 16 andselection transistors (11 b and 11 c) are P-channel transistors, apenetration voltage is generated. This is because potential fluctuationsof the gate signal line 17 a penetrates to a terminal of the capacitor19 via G-S capacitance (parasitic capacitance) of the selectiontransistors (11 b and 11 c). When the P-channel transistor 11 b turnsoff, the voltage is set to Vgh. As a result, the terminal voltage of thecapacitor 19 shifts slightly to the Vdd side. Consequently, the gate (G)terminal voltage of the transistor 11 a rises creating a more intenseblack display. This results in a proper black display.

However, although a completely black display can be achieved in the 0thgradation, it is difficult to display the 1st gradation. In other cases,a large gradation jump may occur between the 0th and 1st gradations orless of insufficient contrast may occur in a particular gradation range.

To solve this problem, a configuration in FIG. 54 is available. Thisconfiguration is characterized by comprising a function to pad outputcurrent values. A main purpose of a padder circuit 541 is to make up forthe penetration voltage. It can also be used to adjust black levels sothat some current (tens of nA) will flow even if image data is at blacklevel 0.

Basically, FIG. 54 is the same as FIG. 48 except that the padder circuithas been added (enclosed by dotted lines in FIG. 54) to the outputstage. In FIG. 54, three bits (K0, K1, and K2) are used as currentpadding control signals. The three bits of control signals make itpossible to add a current value 0 to 7 times larger than the currentvalue of grandchild current sources to output current.

A basic overview of the source driver circuit (IC) 14 according to thepresent invention has been provided above. Now, the source drivercircuit (IC) 14 according to the present invention will be described inmore detail.

The current I (A) passed through the EL element 15 and emissionbrightness B (nt) have a linear relationship. That is, the current I (A)passed through the EL element 15 is proportional to the emissionbrightness B (nt). In current driving, each step (gradation step) isprovided by current (unit transistor 484 (single-unit)).

Human vision with respect to brightness has square-law characteristics.In other words, quadratic brightness changes are perceived to be linearbrightness changes. However, according to the relationship shown in FIG.83, the current I (A) passed through the EL element 15 is proportionalto the emission brightness B (nt) both in low brightness and highbrightness regions. Thus, if brightness is varied step by step (atintervals of one gradation), brightness changes greatly in each step(less of shadow detail occurs) in a low gradation part (black area). Ina high gradation part (white area), since brightness changes coincideapproximately with a linear segment of a quadratic curve, the brightnessis perceived to change at equal intervals. Thus, how to display a blackdisplay area, in particular, becomes a problem in current driving (inwhich each step is provided by an increment of current) (i.e., in acurrent-driven source driver circuit (IC) 14).

To solve this problem, the slope of output current is decreased in thelow gradation region (from gradation 0 (complete black display) togradation R1) and the slope of output current is increased in the highgradation region (from gradation R1 to the highest gradation R). Thatis, a current increment per gradation (in each step) is decreased in thelow gradation region and a current increment per gradation (in eachstep) is increased in the high gradation region. By varying the amountof change in current between the low gradation region and high gradationregion, it is possible to bring gradation characteristics close to aquadratic curve, and thus eliminate less of shadow detail in the lowgradation region.

Incidentally, although two current slopes—in the low gradation regionand high gradation region—are used in the above example, this is notrestrictive. Needless to say, three or more slopes may be used. Needlessto say, however, the use of two slopes simplifies circuit configuration.Preferably, a gamma circuit is capable of generating five or moreslopes.

A technical idea of the present invention lies in the use of two or morevalues of current increment per gradation step in a current-drivensource driver circuit (IC) and the like (basically, circuits which usecurrent outputs for gradation display. Thus, display panels are notlimited to the active-matrix type and include the simple-matrix type).

In EL and other current-driven display panels, display brightness isproportional to the amount of current applied. Thus, the source drivercircuit (IC) 14 according to the present invention can adjust thebrightness of the display easily by adjusting a reference current whichprovides a basis for a current flowing through one current source (oneunit transistor) 484.

In EL display panels, light emission efficiency varies among R, G, and Band color purity deviates from that of the NTSC standard. Thus, toobtain an optimum white balance, it is necessary to optimize ratiosamong R, G, and B. For example the reference current for R is set to 2μA, the reference current for G is set to 1.5 μA, and the referencecurrent for B is set to 3.5 μA. Preferably, at least one referencecurrent out of the reference currents for different colors can bechanged, adjusted, or controlled.

In the case of current driving, the current I passed through the ELelement and brightness have a linear relationship. To adjust whitebalance through a mixture of R, G, and B, it suffices to adjust thereference currents for R, G, and B at only one predetermined brightness.In other words, if the white balance is adjusted by adjusting thereference currents for R, G, and B at the predetermined brightness,basically a white balance can be achieved over the entire range ofgradations. Thus, the present invention is characterized by comprisingadjustment means of adjusting the reference currents for R, G, and B aswell as a single-point polygonal or multi-point polygonal gamma curvegenerator circuit (generating means). The above is a circuit arrangementpeculiar to current-controlled EL display panels.

The gamma circuit of the present invention increments, for example, 10nA per gradation in a low gradation region (corresponding to the slopeof a gamma curve in the low gradation region). In a high gradationregion, it increments 50 nA per gradation (corresponding to the slope ofa gamma curve in the high gradation region).

Incidentally, the ratio of the current increment per gradation in thehigh gradation region to the current increment per gradation in the lowgradation region is referred to as a gamma current ratio. In thisexample, the gamma current ratio is 50 nA/10 nA=5. The gamma currentratio should be equal among R, G, and B. In other words, the current(programming current) flowing through the EL elements 15 is controlledwith the gamma current ratio kept equal among R, G, and B.

Adjusting the gamma current ratio while keeping it equal among R, G, andB makes it easier to configure the circuit. Then it suffices to build,for each of R, G, and B, a constant-current circuit which generates areference current to be applied to the low gradation part andconstant-current circuit which generates a reference current to beapplied to the high gradation part and build (place) a regulator whichadjusts the current passed relatively through the constant-currentcircuits.

FIG. 56 is a block diagram showing a constant-current generating circuitportion for a low gradation part. FIG. 57 is a block diagram showing aconstant-current generating circuit portion for a high gradation partand padder current circuit portion. As shown in FIG. 56, a referencecurrent INL is applied to the low-current source circuit portion.Basically, this current serves as a unit current, the required number ofunit transistors 484 operate according to input data L0 to L4, and thetotal current flows in a low-current portion as a programming currentIwL.

Also, as shown in FIG. 57, a reference current INH is applied to thehigh-current source circuit portion. Basically, this current serves as aunit current, the required number of unit transistors 484 operateaccording to input data H0 to L5, and the total current flows in alow-current portion as a programming current IwH.

The same applies to the padder current circuit portion. As shown in FIG.57, a reference current INH is applied. Basically, this current servesas a unit current, the required number of unit transistors 484 operatesaccording to input data AK0 to AK2, and the total current flows as acurrent IwK which corresponds to a padding current.

The programming current Iw flowing to the source signal line 18 is givenby Iw=IwH+IwL+IwK. The ratio of IwH to IwL, i.e., the gamma currentratio should satisfy the relationship described earlier.

As illustrated in FIGS. 56 and 67, the on/off switch 481 consists of aninverter 562 and an analog switch 561 which in turn consists of aP-channel transistor and N-channel transistor. This configuration canreduce on-resistance and minimize voltage drops between the unittransistor 484 and the source signal line 18. Needless to say, this alsoapplies to other examples of the present invention.

Now, description will be given of the low-current circuit portion inFIG. 56 and high-current circuit portion in FIG. 57. The source drivercircuit (IC) 14 according to the present invention consists of 5 bits—L0to L4—in the low-current circuit portion and 6 bits—H0 to H5—in thehigh-current circuit portion. Incidentally, the data fed into thecircuits consists of 6 bits D0 to D5 (64 gradations for each color). The6-bit data is converted into 5-bit data—L0 to L4—and 6-bit data—H0 toH5—in the high-current circuit portion and the programming current Iwcorresponding to image data is applied to the source signal line. Thatis the 6-bit data is converted into 11-bit data (=5+6). This makes itpossible to form a high-accuracy gamma curve.

As described above, the 6-bit input data is converted into 11-bit data(=5+6). According to the present invention, the bit count (H) in thehigh-current region of the circuit is equal to the bit count of inputdata (D) while the bit count (L) in the low-current region of thecircuit is equal to the bit count of input data (D) minus 1.Incidentally, the bit count (L) in the low-current region of the circuitmay be the bit count of input data (D) minus 2. This configurationoptimizes the gamma curve in the low-current region and gamma curve inthe high-current region for image display on the EL display panel.

The gate driver circuit 12 is normally composed of N-channel andP-channel transistors. Preferably, however, it is composed solely ofP-channel transistors because this will reduce the number of masksrequired for the production of arrays, improve production yields, andimprove throughput. Thus, as illustrated in FIGS. 1, 2, and the like,P-channel transistors should be used for the pixels 16 as well as forthe gate driver circuits 12. Ten masks are required when a gate drivercircuit is composed of N-channel and P-channel transistors, but fivemasks are required when a gate driver circuit is composed solely ofP-channel transistors.

However, if the gate driver circuit 12 and the like are composed solelyof P-channel transistors, a level shifter circuit, which is composed ofN-channel and P-channel transistors, cannot be formed on the array board71.

Description will be given below of the gate driver circuit 12 accordingto the present invention, where the gate driver circuit 12, which isbuilt into the array board 71, is composed solely of P-channeltransistors. As described above, by using only P-channel transistors forthe pixels 16 as well as for the gate driver circuits 12 (i.e., all thetransistors formed on the array board 71 are P-channel transistors. Toput it in other words, no N-channel transistor is used), it is possibleto reduce the number of masks required for the production of arrays,improve production yields, and improve throughput. Also, it is possibleto concentrate on improving the performance of the P-channeltransistors, consequently making it easy to improve characteristics. Forexample, it is easier to lower Vt (threshold voltage) (bring the Vtcloser to 0 V) and reduce variations in the Vt than in the case of CMOSstructure (structure which employs both P-channel and N-channeltransistors).

Examples of the present invention are described by citing mainly thepixel configuration in FIG. 1, but this is not restrictive. Needless tosay, other pixel configurations may also be used. Also, theconfiguration and layout of the gate driver circuit 12 described beloware not limited to self-luminous devices such as organic EL displaypanels. They can also be used for liquid crystal display panels,electromagnetic display panels, FEDs (field emission displays), etc. Forexample, liquid crystal display panels may employ the configuration orarrangement of the gate driver circuit 12 according to the presentinvention to control a pixel's selection switching element. If twophases of the gate driver circuits 12 are used, one phase may be used toselect a pixel's switching element and the other phase may be connectedto one terminal of a retention capacitance in the pixel. This scheme isreferred to as independent CC driving. Needless to say, theconfigurations described with reference to FIGS. 71, 73, etc. can alsobe used not only for the gate driver circuit 12, but also for the shiftregister circuits of the source driver circuit 14.

FIG. 71 is a block diagram of the gate driver circuit 12 according tothe present invention. Although only four stages are illustrated forease of explanation, basically there are as many unit gate outputcircuits 711 as there are gate signal lines 17.

As illustrated in FIG. 71, the gate driver circuits 12 (12 a and 12 b)according to the present invention comprise signal terminals: four clockterminals (SCK0, SCK1, SCK2, and SCK3), one start terminal (data signalSSTA), and two inverting terminals (DIRA and DIRB which apply signals180 degrees out of phase with each other) which turn a shift directionupside down. They also comprise power supply terminals, including an Lpower supply terminal (VBB) and H power supply terminal (Vd).

If the pixels 16 are composed of P-channel transistors, they match wellwith the gate driver circuits 12 composed of P-channel transistors. TheP-channel transistors (the transistors 11 b, 11 c, and 11 d in theconfiguration shown in FIG. 1) turn on at L voltage. The gate drivercircuits 12 also use the L voltage as a selection voltage. As can beseen also from the configuration in FIG. 73, gate drivers composed ofP-channel transistors match well if the L level is used as a selectionlevel. This is because the L level cannot be maintained for a longperiod. On the other hand, H voltage can be maintained for a longperiod.

If a P-channel transistor is used as the driver transistor (thetransistor 11 a in the configuration shown in FIG. 1) which suppliescurrent to the EL element 15, the cathode of the EL element 15 can beformed into a solid electrode of a thin metal film. Also, current can bepassed in the forward direction to the EL element 15 from the anodepotential Vdd. Thus, preferably P-channel transistors are used as thetransistors of the pixels 16 and the transistors of the gate drivercircuits 12. Thus, the use of P-channel transistors as the transistors(driver transistors and switching transistors) of the pixels 16according to the present invention and the transistors of the gatedriver circuits 12 is not simply a design matter.

Incidentally, the level shifter (LS) circuit may be formed directly onthe array board 71. That is, level shifter (LS) is constructed from bothN-channel and P-channel transistors. A logic signal from a controller(not shown) is boosted by the level shifter (LS) circuit formed directlyon the array board 71 so that it will match the logic level of the gatedriver circuit 12 constructed from a P-channel transistor. The boostedlogic voltage is applied to the gate driver circuit 12.

Incidentally, the level shifter circuit may be constructed from asilicon chip and mounted on the array board 71 using COG technology.Also, the source driver circuit 14 is constructed from a silicon chipand mounted on the array board 71 using COG technology. However, this isnot restrictive and the source driver circuit 14 may be formed directlyon the array board 71 using polysilicon technology.

If P-channel transistors are used as the transistors 11 of the pixel 16,the programming current flows out from the pixel 16 to the source signalline 18. Thus, the unit current circuits 484 (see FIGS. 56, 57, etc.) ofthe source driver circuit must be N-channel transistors. In other words,the source driver circuit 14 should be configured to draw theprogramming current Iw.

Thus, if the driver transistors 11 a of the pixels 16 (in the case ofFIG. 1) are P-channel transistors, the unit transistors 484 of thesource driver circuits 14 must be N-channel transistors to ensure thatthe source driver circuits 14 will draw the programming current Iw. Inorder to form a source driver circuit 14 on an array board 71, it isnecessary to use both mask (process) for N-channel transistors and mask(process) for P-channel transistors. Conceptually speaking, in thedisplay panel (display apparatus) of the present invention, P-channeltransistors are used for the pixels 16 and gate driver circuits 12 whileN-channel transistors are used as the transistors of drawing currentsources of the source drivers.

Thus, P-channel transistors are used as the transistors 11 of the pixels16 and the transistors of the gate driver circuits 12. This makes itpossible to reduce the costs of the array board 71. However, the unittransistors 484 of the source driver circuits 14 must be N-channeltransistors. Consequently, the source driver circuit 14 cannot be formeddirectly on the array board 71. Thus, the source driver circuits 14 aremade of silicon chips and the like separately and mounted on the arrayboard 71. Incidentally, it is not always necessary to construct thesource driver circuits 14 from silicon chips. For example, a largenumber of source driver circuits may be formed on a glass substratesimultaneously using low-temperature polysilicon technology or the like,cut off into chips, and mounted on an array board 71. Incidentally,although it has been stated that source driver circuits are mounted onan array board 71, this is not restrictive. Any form may be adopted aslong as the output terminals 681 of the source driver circuits 14 areconnected to the source signal lines 18 of the array board 71. Forexample, the source driver circuits 14 may be connected to the sourcesignal lines 18 using TAB technology, By forming source driver circuits14 on a silicon chip separately, it is possible to reduce variations inoutput current and achieve proper image display as well as to reducecosts.

The configuration in which P-channel transistors are used as selectiontransistors of pixels and for gate driver circuits is not limited toorganic EL or other self-luminous devices (display panels or displayapparatus). For example, it is also applicable to liquid crystal displaypanels and FEDs (field emission displays).

The inverting terminals (DIRA and DIRB) apply common signals to all theunit gate output circuits 711. As can be seen from an equivalent circuitdiagram in FIG. 73, inverting terminals (DIRA and DIRB) are fed voltagevalues of opposite polarity. To reverse the scan direction of the shiftregister, the polarity of the voltage values fed into the invertingterminals (DIRA and DIRB) is reversed.

Incidentally, the circuit configuration in FIG. 71 contains four clocksignal lines. Four is the optimum number according to the presentinvention. However, this is not restrictive and the present inventionmay use less than or more than four clock signal lines.

The clock signals (SCK0, SCK1, SCK2, and SCK3) are fed differentlybetween adjacent unit gate output circuits 711. For example, in the unitgate output circuit 711 a, OC is fed by the clock terminal SCK0 whileRST is fed by the clock terminal SCK2. This is also the case with theunit gate output circuit 711 c. However, in the unit gate output circuit711 b (the unit gate output circuit in the next stage) adjacent to theunit gate output circuit 711 a, OC is fed by the clock terminal SCK1while RST is fed by the clock terminal SCK3. In this way, every otherunit gate output circuit 711 is fed by clock terminals in a differentmanner: OC is fed by SCK0 and RST is fed by SCK2, OC is fed by SCK1 andRST is fed by SCK3 in the next stage, OC is fed by SCK0 and RST is fedby SCK2 in the next stage, and so on.

FIG. 73 shows a circuit configuration of the unit gate output circuit711, which uses only P-channel transistors. FIG. 74 is a timing chartfor use to explain the circuit configuration of FIG. 73. FIG. 72 is atiming chart of multiple stages in FIG. 73. Thus, by understanding FIG.73, it is possible to understand overall operation. Rather than beingexplained in text, the operation can be understood with reference to thetiming chart in FIG. 74 in conjunction with the equivalent circuitdiagram in FIG. 73, and thus detailed description of transistoroperation will be omitted.

When driver circuits are built solely of P-channel transistors, it isbasically difficult to maintain the gate signal lines 17 at an H level(Vd voltage in FIG. 73). It is also difficult to maintain them at an Llevel (VBB voltage in FIG. 73) for a long period of time, but they canbe kept adequately at the H level for a short period such as duringselection of a pixel row.

If the switching transistors 11 b and 11 c of a pixel 16 are P-channeltransistors, the pixel 16 becomes selected at Vgh, and becomesdeselected at Vgl. As described earlier, when the gate signal line 17 achanges from Vgl (on) to Vgh (off), voltage penetrates (penetrationvoltage). If the driver transistor 11 a of the pixel 16 is a P-channeltransistor, the penetration voltage restricts the flow of currentthrough the transistor 11 a in black display mode. This makes itpossible to achieve a proper black display. The problem with thecurrent-driven system is that it is difficult to achieve a blackdisplay. However, if P-channel transistors are used for the gate drivercircuits 12, the turn-on voltage corresponds to Vgh. Thus, the gatedriver circuits 12 match well with the pixels 16 constructed fromP-channel transistors. Also, it is important that the programmingcurrent Iw flows from the anode voltage Vdd to the unit transistors 484of the source driver circuits 14 via the driver transistors 11 a andsource signal lines 18, as is the case with the pixel 16 configurationshown in FIGS. 1, 2, 32, 113, and 116. Thus, a good synergistic effectcan be produced if P-channel transistors are used for the gate drivercircuits 12 and pixels 16, the source driver circuits 14 are mounted onthe substrate, and N-channel transistors are used as the unittransistors 484 of the source driver circuits 14. Besides, unittransistors 484 constituted of N-channel transistors have smallervariations in output current than unit transistors 484 constituted ofP-channel transistors.

The same applies to FIG. 42(b). FIG. 42(b) shows a configuration inwhich a programming current Iw flows from an anode voltage Vdd to theunit transistors 484 of a source driver circuit 14 via a programmingtransistor 11 a and source signal line 18 rather than a configuration inwhich current flows into the unit transistors 484 of a source drivercircuit 14 via a driver transistor 11 b. Thus, as in the case of FIG. 1,a good synergistic effect can be produced if P-channel transistors areused for the gate driver circuits 12 and pixels 16, the source drivercircuits 14 are mounted on the substrate, and N-channel transistors areused as the unit transistors 484 of the source driver circuits 14.

A signal fed to an IN terminal and the SCK clock fed to the RST terminalinvert the state of n1 with respect to n2. Although n2 and n4 havepotentials of the same polarity, the SCK clock fed to the OC terminallowers the potential level of n4 further. In contrast, a Q terminal iskept at the L level for the same period (a turn-on voltage is outputfrom the gate signal line 17). A signal outputted to an SQ terminal orthe Q terminal is transferred to the unit gate output circuit 711 in thenext stage.

In the circuit configuration in FIGS. 71 and 73, by controlling the IN(INA and INB) terminals and the timings of signal application to clockterminals, it is possible to two modes using the same circuitconfiguration: a mode in which one gate signal line 17 is selected asshown in FIG. 75(a) and a mode in which two gate signal lines 17 areselected as shown in FIG. 75(b).

In the selection-side gate driver circuit 12 a, FIG. 75(a) shows a drivemode in which pixel rows are selected one (51 a) at a time (normaldriving) shifting on a row-by-row basis. FIG. 75(b) shows aconfiguration in which two pixel rows are selected at a time. This drivemode corresponds to the driving for simultaneous selection of multiplepixel rows (51 a and 51 b) described with reference to FIGS. 27, 28, and29 (configuration in which a dummy pixel row is used). Two adjacent rowsare selected at a time shifting on a row-by-row basis. According to thedrive method in FIG. 75(b) in particular, while the pixel row (51 a)holds final video, the pixel row 51 b is precharged. This makes thepixel 16 easier to write into. That is, the present invention can switchbetween two drive modes by manipulating signals applied to terminals.

Incidentally, although 75(b) shows a mode in which adjacent rows ofpixels 16 are selected, it is also possible to select rows of pixels 16other than adjacent pixel rows (FIG. 76 shows an example in which pixelrows three pixel rows apart are selected). In the configuration shown inFIG. 73, pixel rows are controlled in sets of four. Out of four pixelrows, it is possible to determine whether to select one pixel row or twoconsecutive pixel rows. The number of pixel rows in each set isrestricted by the number of clocks (SCK), which is four in this case. Ifeight clocks (SCK) are used, pixel rows can be controlled in sets ofeight.

Operation of the selection-side gate driver circuit 12 a is shown inFIG. 75. In FIG. 75(a), one pixel row is selected at a time andselection position is shifted by one pixel row in sync with a horizontalsynchronization signal. In FIG. 75(b), two pixel rows are selected at atime and selection position is shifted by one pixel row in sync with ahorizontal synchronization signal.

With reference to drawings, description will be given below of ahigh-quality display method based on current driving (currentprogramming). Current programming involves applying current signals tothe pixels 16 and making the pixels 16 retain the current signals. Thenthe retained current is applied to the EL elements 15.

The EL elements 15 emit light in proportion to the applied current. Thatis, the emission brightness of the EL elements 15 has a linearrelationship with programmed current. On the other hand, in the case ofvoltage programming, applied voltage is converted into current in thepixels 16. The voltage-current conversion is non-linear. Non-linearconversion involves a complicated control method.

In current programming, values of video data are converted directly intoprogramming current linearly. To take a simple example, in the case of64 gradation display, video data 0 is converted into a programmingcurrent Iw=0 μA and video data 63 is converted into a programmingcurrent Iw=6.3 μA (proportionality exists). Similarly, video data 32 isconverted into a programming current Iw=3.2 μA and video data 10 isconverted into a programming current Iw=1.0 μA. In short, video data areconverted into programming current in direct proportion.

For ease of understanding, it has been stated that video data areconverted into programming current in direct proportion. Actually,however, video data can be converted into programming current moreeasily. This is because according to the present invention, a unitcurrent of the unit transistor 484 corresponds to video data 1 asillustrated in FIG. 48. Furthermore, the unit current can be adjustedeasily to a desired value by adjusting reference current circuits.Besides, separate reference currents are provided for R, G, and Bcircuits and a white balance can be achieved over the entire gradationrange by adjusting the R, G, and B reference current circuits. This is aresult of synergy among current programming, the source driver circuits14 of the present invention, and the configuration of the display panel.

EL display panels are characterized in that the emission brightness ofthe EL elements 15 has a linear relationship with programming current.This is a major feature of current programming. Thus, if the magnitudeof the programming current is controlled, the emission brightness of theEL elements 15 can be adjusted linearly.

The relationship between the voltage applied to the gate terminal of thedriver transistor 11 a and the current passed through the drivertransistor 11 a is non-linear (often results in a quadratic curve).Therefore, in voltage programming, there is anon-linear relationshipbetween programming voltage and emission brightness, making it extremelydifficult to control light emission. In contrast, current programmingmakes light emission control extremely easy. In particular, with theconfiguration shown in FIG. 1, the programming current is theoreticallyequal to the current flowing through the EL element 15. This makes lightemission control extremely easy to understand and easy to control. TheN-fold pulse driving according to the present invention also excels inlight emission control because the emission brightness can be determinedby dividing the programming current by N. If pixels have acurrent-mirror configuration as in the case of FIG. 38, the drivertransistor 11 b and programming transistor 11 a are different, whichcauses a deviation in the current mirror ratio, introducing an errorfactor into emission brightness. However, the pixel configuration inFIG. 1, in which the driver transistor and programming transistor areidentical, is free of this problem.

The emission brightness of the EL element 15 changes in proportion tothe amount of supplied current. The value of the voltage (anode voltage)applied to the EL element 15 is fixed. Therefore, emission brightness ofthe EL display panel is proportional to power consumption.

Thus, video data is proportional to programming current, which isproportional to the emission brightness of the EL element 15, which inturn is proportional to power consumption. Therefore, by performinglogic processes on the video data, it is possible to control the powerconsumption (power), emission brightness, and power consumption of theEL display panel. That is, by performing logic processes (addition,etc.) on the video data, it is possible to determine the brightness andpower consumption of the EL display panel. This makes it extremely easyto prevent peak current from exceeding a set value.

In particular, the EL display panel of the present invention is acurrent-driven type. In addition, characteristic configuration makes iteasy to control image display. There are two characteristic imagedisplay control method. One of them is reference current control. Theother is duty cycle control. The reference current control and dutycycle control, when used singly or in conjunction, can achieve a widedynamic range, high-quality display, and high contrast.

To begin with, regarding reference current control, the source drivercircuit (IC) 14 is equipped with circuits which control RGB referencecurrents, as illustrated in FIG. 77. The magnitude of the programmingcurrent Iw flowing from the source driver circuit 14 to the unittransistors 484 depends on the number of the unit transistors 484.

The current outputted by one unit transistor 484 is proportional to themagnitude of the reference current. Thus, as the reference current isadjusted, the current outputted by one unit transistor 484 and themagnitude of the programming current are determined. The referencecurrent and the output current of the unit transistor 484 have a linearrelationship and the programming current and brightness have a linearrelationship. Therefore, if the RGB reference currents and white balanceare adjusted in white raster display, the white balance can bemaintained for all gradations.

Incidentally, although the current mirrors in FIG. 77 have multi-stageconnections, the present invention is not limited to this. Needless tosay, even the single-stage source driver circuits (ICs) 14 shown in FIG.166 to 170 can easily adjust reference currents and maintain whitebalance over all the gradations. Also, it goes without saying that thebrightness of the EL display panel can be controlled through adjustmentof the reference currents.

FIG. 78 shows duty cycle control methods. FIG. 78(a) shows a method ofinserting a non-display area 52 continuously. This method is suitablefor movie display. The image in FIG. 78(a 1) is the darkest and theimage in FIG. 78(a 4) is the brightest. The duty ratio can be changedeasily through control of the gate signal line 17 b. FIG. 78(c) shows amethod of inserting a non-display area 52 by dividing it into multipleparts. This method is suitable especially for still picture display. Theimage in FIG. 78(c 1) is the darkest and the image in FIG. 78(c 4) isthe brightest. The duty ratio can be changed easily through control ofthe gate signal line 17 b. FIG. 78(b) shows something in between FIG.78(a) and FIG. 78(c). Again, the duty ratio can be changed easilythrough control of the gate signal line 17 b.

If the number of pixel rows is 220 and the duty ratio is 1/4, since220/4=55, the brightness of the display area 53 can be varied from 1 to55 (from brightness 1 to 55 times the brightness 1). Also, if the numberof pixel rows is 220 and the duty ratio is 1/2, since 220/2=110, thebrightness of the display area 53 can be varied from 1 to 110 (frombrightness 1 to 110 times the brightness 1). Thus, the adjustable rangeof the screen brightness 50 is very wide (the dynamic range of imagedisplay is wide). Also, the number of gradations which can be expressedis the same at any brightness. For example, in the case of 64 gradationdisplay, 64 gradations can be displayed whether the brightness of thescreen 50 in white raster display is 300 nt or 3 nt.

As described earlier, the duty ratio can be changed easily throughcontrol of the start pulse applied to the gate driver circuit 126. Thus,it can be easily changed to any of various values, including 1/2, 1/4,3/4, and 3/8.

Duty ratio driving based on a unit duration of one horizontal scanningperiod (1 H) can be achieved by the application of on/off signals to thegate signal line 17 b in sync with a horizontal synchronization signal.However, duty cycle control can also be performed using a unit durationshorter than 1 H. Such drive methods are shown in FIGS. 145 and 146.Brightness (duty ratio) can be controlled in fine steps throughOEV2-based control at intervals of 1 H or less (see also FIGS. 109 and175 and their description).

Duty cycle control at intervals of 1 H or less should be performed whenthe duty ratio is 1/4. If the number of pixel rows is 200, the dutyratio is 55/220 or less. That is, the duty cycle control should beperformed with a duty ratio in the range of 1/220 to 55/220. It shouldbe performed when a single step causes a change of 1/20 (5%) or more.More preferably, fine duty ratio driving control should be performedusing OEV2-based control even if a single change is 1/50 (2%) or less.That is, in the duty cycle control by means of the gate signal line 17b, if a single step produces a brightness change of 5% or more,OEV2-based control should be used to change brightness little by littlein such a way as to keep the amount of single change within 5%.Preferably, this is done using a Wait function described with referenceto FIG. 94.

In duty cycle control at a duty ratio of 1/4 and at intervals of 1 H orless, a single step produces a large change. Besides, even minutechanges tend to be perceived visually due to halftone image display.Human vision has low detection capability with respect to brightness ona screen darker than a certain level. Also, it has low detectioncapability with respect to brightness changes on a screen brighter thana certain level. It is believed that this is because human vision hassquare-law characteristics.

FIG. 174 shows a graphic plot of a detection function against changes ona screen. The horizontal axis represents screen brightness (nt) whilethe vertical axis represents permissible change (%). The permissiblechange (%) represents tolerance limits to the rate of brightness changewhich results when the duty ratio is changed from an arbitrary value tothe next value. However, the permissible change (%) depends heavily onimage content (the rate of change, scene, etc.). Also, it tends todepend on individual capability for movie detection.

As can be seen from FIG. 174, when the brightness of the screen 50 ishigh, the permissible duty ratio change is large. When the brightness ofthe screen 50 is low, the permissible duty ratio change also tends to belarge. However, in the case of halftone display, the tolerance limits interms of the permissible change (%) are small. This is because inhalftone images, even minute changes tend to be perceived visually.

To take an example, if the number of pixel rows in the panel is 200,duty cycle control is performed at intervals of 1 H or less usingOEV2-based control at a duty ratio of 50/200 or less (from 1/200 to50/200 both inclusive). When the duty ratio changes from 1/200 to 2/200,the difference between 1/200 and 2/200 is 1/200, meaning a 100% change.This change is fully perceived visually as flickering. Thus, the currentsupply to the EL elements 15 is controlled by OEV2-based control (seeFIG. 175, etc.) at intervals of 1 H (one horizontal scanning period) orless. Incidentally, although it has been stated that duty cycle controlis performed at intervals of 1 H or less, this is not restrictive. Ascan be seen from FIG. 19, the non-display area 52 is continuous. Thismeans that control at intervals of 10.5 Hs is also included in the scopeof the present invention. Thus, the present invention performs dutycycle control at intervals which is not limited to 1 H (and which maycontain a decimal part).

When the duty ratio changes from 40/200 to 41/200, the differencebetween 40/200 and 41/200 is 1/200, meaning a (1/200)/(40/200) or 2.5%change. Whether this change is perceived visually as flickering ishighly likely to depend on the brightness of the screen 50. However, theduty ratio of 40/200 means a halftone display, which is related to highvisual sensitivity. Thus, it is desirable to control the current supplyto the EL elements 15 by means of OEV2-based control (see FIG. 175,etc.) at intervals of 1 H (one horizontal scanning period) or less.

Thus, the drive method and display apparatus of the present inventiongenerate at least the display mode shown in FIG. 19 for display images(the display area 53 may occupy the entire screen 50 (meaning a dutyratio of 1/1 depending on the brightness of the images) in a displaypanel comprising means (e.g., the capacitor 19 in FIG. 1) of storing thevalues of current to be passed through the EL elements 15 in the pixels16 and means (e.g., the pixel configuration in FIG. 1, 43, 113, 114,117, or the like) of turning on and off the current paths between thedriver transistors 11 a and light-emitting elements (e.g., the ELelements 15). Also, in duty ratio driving (a drive method or drive modein which at least part of the screen 50 is occupied by a non-displayarea 53) at a duty ratio not higher than a predetermined value, thedrive method and display apparatus of the present invention control thebrightness of the screen 50 by controlling the current passed throughthe EL elements 15 for a unit duration of one horizontal scanning period(period of 1 H) or less. This control uses OEV2-based control (for OEV2,see FIG. 175 and its description).

Duty cycle control based on a unit duration of other than 1 H should beperformed when the duty ratio is 1/4. Conversely, when the duty ratio isnot lower than a predetermined value, duty cycle control should beperformed using a unit duration of 1 H or no OEV2-based control shouldbe performed. Duty cycle control using a unit duration of other than 1 Hshould be performed when a single step causes a change of 1/20 (5%) ormore. More preferably, fine duty ratio driving control should beperformed using OEV2-based control even if a single change is 1/50 (2%)or less. Alternatively, it should be performed at a brightness 1/4 themaximum brightness of white raster.

The duty cycle control driving according to the present invention allowsan EL display panel capable of, for example, 64-gradation display tomaintain 64-gradation display regardless of the display brightness (nt)of the screen 50, as illustrated in FIG. 79. For example, even if thenumber of pixel rows is 220 and only one pixel row constitutes a displayarea 53 (is in display mode) (the duty ratio is 1/220), a 64-gradationdisplay can be achieved. This is because images are written into oneafter another of pixel rows by the programming current Iw from thesource driver circuits 14 and the images are displayed by one afteranother of the pixel rows.

Of course, when all the 220 pixel rows constitute a display area 53 (arein display mode) (the duty ratio is 220/220=1/1), a 64-gradation displaycan be achieved as well. This is because images are written into oneafter another of pixel rows by the programming current Iw from thesource driver circuits 14 and the images carried by all the pixel rowsare displayed at once by the gate signal lines 17 b. Also, when only 20pixel rows constitute a display area 53 (are in display mode) (the dutyratio is 20/220=1/11), a 64-gradation display can be achieved as well.This is because images are written into one after another of pixel rowsby the programming current Iw from the source driver circuits 14 and theimages are displayed as the 20 pixel rows are scanned one after anotherby the gate signal lines 17.

Since the duty cycle control driving according to the present inventioncontrols the illumination time of the EL elements 15, there is a linearrelationship between the duty ratio and screen 50 brightness. This makesit extremely easy to control image brightness, simplify signalprocessing circuits, and reduce costs. As shown in FIG. 77, the RGBreference currents are adjusted to achieve a white balance. In dutycycle control, since RGB brightness is controlled simultaneously, whitebalance is maintained at any gradation and at any screen 50 brightness.

Duty cycle control consists in varying the brightness of the screen 50by varying the size of the display area 53 in relation to the screen 50.Naturally, current flows through the EL display panel in approximateproportion to the display area 53. Therefore, by determining the sum ofvideo data, it is possible to calculate the total current consumption ofthe EL elements 15 of the display screen 50. Since the anode voltage Vddof the EL elements 15 is a direct voltage and its value is fixed, if thetotal current consumption can be calculated, total power consumption canbe calculated in real time according to image data. If the calculatedtotal power consumption is expected to exceed prescribed maximum power,the RGB reference currents in FIG. 77 can be controlled throughadjustment of a regulator circuit such as an electronic regulator.

Brightness is preset during white raster display in such a way as tominimized the duty ratio at this time. For example, the duty ratio isset to 1/8. The duty ratio is increased for natural images. The maximumduty ratio is 1/1. The duty ratio available when a natural image isdisplayed in only 1/100 of the screen 50 is taken as 1/1. The duty ratiois varied smoothly from 1/1 to 1/8 based on display condition of naturalimages.

Thus, as an example, the duty ratio is set to 1/8 during white rasterdisplay (a state in which 100% of the pixels are illuminated in whiteraster display) and is set to 1/1 when 1/100 of the pixels on the screen50 are illuminated. The duty ratio can be calculated approximately usingthe formula: “the number of pixels”×“ratio of illuminated pixels”×“dutyratio.”

If it is assumed for ease of explanation that the number of pixels is100, the power consumption for white raster display is 100×1 (100%)×1/8(duty ratio)=80. On the other hand, the power consumption for naturalimage display for which 1/100 of pixels illuminate is 100×1/100 (1%)×1/1(duty ratio)=1. The duty ratio is varied smoothly from 1/1 to1/8according to the number of illuminated pixels of images (actually,total current drawn by illuminated pixels=sum total of programmingcurrents per frame) so that no flickering will occur.

Thus, the power consumption ratio for white raster display is 80 and thepower consumption ratio for natural image display for which 1/100 ofpixels illuminate is 1. Therefore, by presetting a brightness duringwhite raster display in such away as to minimized the duty ratio at thistime, it is possible to reduce the maximum current.

The present invention performs drive control using S×D, where S is thesum total of programming currents per screen and D is a duty ratio.Also, the present invention provides a drive method which maintains arelationship Sw×Dmin≧Ss×Dmax as well as a display apparatus whichimplements the drive method, where Sw is the sum total of programmingcurrents for white raster display, Dmax is the maximum duty ratio(normally, the maximum duty ratio is 1/1), Dmin is the minimum dutyratio, and Ss is the sum total of programming currents for an arbitrarynatural image.

Incidentally, it is assumed that the maximum duty ratio is 1/1.Preferably, the minimum duty ratio is 1/16 or above. That is, the dutyratio should be from 1/8tol/1 (both inclusive) Needless to say, it isnot strictly necessary to use the duty ratio of 1/1. Preferably, theminimum duty ratio is 1/10 or above. To small a duty ratio makesflickering conspicuous as well as causes screen brightness to varygreatly with the image content, making the image hard to see.

As described earlier, programming current is proportional to video data.Thus, “the sum total of programming currents” is synonymous with “thesum total of programming currents.” Incidentally, although it has beenstated that the sum total of programming currents is determined over oneframe (field) period, this is not restrictive. It is also possible todetermine the sum total of programming currents (video data) by samplingpixels which add to programming currents at predetermined intervals oron a predetermined cycle during one frame (field) period. Alternatively,it is also possible to use the total sum before and after the frame(field) period to be controlled. Also, an estimated or predicted totalsum may be used for duty cycle control.

Incidentally, it has been stated that the duty ratio D is used forcontrol, the duty ratio is an illumination period of the EL element 15(normally one field or one frame. In other words, this is generally acycle or time during which image data of a given pixel is rewritten).Specifically, a duty ratio of 1/8 means that the EL element 15illuminates for 1/8 of one frame period (1F/8). Thus, if the cycle/timeduring which the pixel 16 is rewritten is denoted by Tf and theillumination period of the pixel is denoted by Ta, the duty ratio isgiven by duty ratio=Ta/Tf.

Incidentally, although it has been stated that Tf denotes the cycle/timeduring which the pixel 16 is rewritten and that Tf is used as areference, this is not restrictive. The duty cycle control drivingaccording to the present invention does not need to complete in oneframe or one field. That is, the duty cycle control may be performedusing a few fields or few frame periods as one cycle (see FIG. 104,etc.). Thus, Tf is not limited to the cycle during which the pixel 16 isrewritten. It may be one frame/field or more. For example, if theillumination period Ta varies from field to field (or from frame toframe), the total illumination period Ta during a repetition cycle(period) Tf may be adopted. That is, average illumination time over afew fields or few frame periods may be used as Ta. The same applies tothe duty ratio. If the duty ratio varies from field to field (or fromframe to frame) the average duty ratio over a few frames (fields) may becalculated and used.

Thus, the present invention provides a drive method which maintains arelationship Sw×(Tas/Tf)≧Ss×(Tam/Tf) as well as a display apparatuswhich implements the drive method, where Sw is the sum total ofprogramming currents for white raster display, Ss is the sum total ofprogramming currents for an arbitrary natural image, Tas is the minimumillumination period, and Tam is the maximum illumination period(normally, Tam=Tf, and thus Tam/Tf=1).

As a method of controlling the brightness of the screen 50, theconfiguration described with reference to FIG. 77 and the like isavailable. To vary the screen brightness 50, this method adjustsreference current, thereby varying the current flowing through the unittransistor 634, and thereby adjusting the magnitude of the programmingcurrent. Incidentally, the method of adjusting reference current hasbeen described with reference to FIG. 53 and the like.

Referring to FIG. 77, reference numeral 491R denotes a regulator used tocontrol reference current for red (R). The term “regulator” is used forease of understanding. Actually, this component is called an electronicregulator. It is configured to adjust reference current IaR for an Rcircuit linearly in 64 steps in response to a 6-bit digital signal fromoutside. By adjusting the reference current IaR, it is possible tolinearly vary the current flowing through a transistor 472 a whichconstitutes a current mirror with a transistor 471R. This changes to thecurrent flowing through a transistor 472 b which has received acurrent-based delivery from the transistor 472 a in a transistor group521 a. This in turn causes changes to a transistor 473 a in a transistorgroup 521 b which constitutes a current mirror with the transistor 472b, resulting in changes to a transistor 473 b which has received acurrent-based delivery from the transistor 473 a. Thus, since the drivecurrent (unit current) of the unit transistor 484 changes, theprogramming current can be changed. Incidentally, the same applies toreference current IaG for G and reference current IaB for B.

Although FIG. 77 shows a three-stage transistor connections consistingof a parent, children, and grandchildren, the present invention is notlimited to this. Needless to say, the present invention is alsoapplicable, for example, to a single-stage configuration in which acircuit which generates reference current is directly connected to unittransistors 484 as shown in FIGS. 166 to 170. That is, the presentinvention is a system which varies the brightness of the screen 50 usingreference current or reference voltage in a circuit configuration inwhich programming current or programming voltage can be varied by areference current or reference voltage.

As shown in FIG. 77, an (electronic) regulator 491 is formed for each ofred (R), green (G), and blue (B) circuits. Thus, by regulating theregulators 491R, 491G, and 491B, it is possible to vary (control oradjust) the current on the unit transistors 484 connected to therespective regulators. Thus, white (W) balance can be adjusted easilythrough adjustment of the ratio among R, G, and B. Of course, if the RGBreference currents (currents which flow through transistors 472R, 472G,and 472B) have been adjusted at the factory, by separately installing anelectronic regulator which can control the RGB electronic regulators(491R, 491G, and 491B) all at once, it is possible to adjust the white(W) balance as well. For example, in FIGS. 169 and 170, the value ofresistance R1 is adjusted so as to achieve a white balance in the RGBcircuits. In this state, if switches of the electronic regulator 451 inFIGS. 169 and 170 are operated commonly for R, G, and B, the screenbrightness can be adjusted with the white balance maintained.

In this way, the drive method of reference current according to thepresent invention adjusts the values of RGB reference currents byachieving a white balance. Then, based on this state, the drive methodadjusts the RGB reference currents at the same ratio. For that, thewhite balance is maintained.

Through the adjustment of the electronic regulators 491, the programmingcurrent can be varied linearly. Incidentally although the pixelconfiguration shown in FIG. 1 is cited as an example for ease ofexplanation, the present invention is not limited to this. Needless tosay, other pixel configurations may be used as well.

As illustrated in, or described with reference to, FIG. 77, theprogramming current can be adjusted linearly through control of thereference current. This is because the output current of each unittransistor 484 changes. As the output current of the unit transistor 484is varied, the programming current Iw changes as well. The larger thecurrent (actually, the voltage which corresponds to the programmingcurrent) programmed into the capacitor 19 of a pixel, the larger thecurrent flowing through the EL element 15. The current flowing throughthe EL element is linearly proportional to emission brightness. Thus, byvarying the reference current, it is possible to vary the emissionbrightness of the EL element linearly.

The present invention controls screen brightness and the like using atleast either the reference current control system described withreference to FIG. 77 or the duty cycle control system described withreference to FIG. 78. Preferably, both systems are used in combination.

Drive methods which employ the systems described with reference to FIGS.77 and 78 will be described below in more detail. One object of thepresent invention is to place an upper limit on the current consumptionof EL display panels. In EL display panels, there is proportionalitybetween the current flowing through the EL element 15 and emissionbrightness. Thus, by increasing the current flowing through the ELelement 5, the EL display panel can be made ever brighter. The currentconsumed (=current consumption) also increases in proportion to thebrightness.

In the case of portable apparatus, there are limits to battery capacityand the like. Also, a power supply circuit increases in scale withincreases in current consumption. Thus, it is necessary to place limitson current consumption. It is an object of the present invention toplace such limits (peak current control).

Also, increasing image contrast improves display. By converting imagesinto high-contrast images, it is possible to improves display. It isanother object of the present invention to improve image display in thisway. An invention which achieves the two objects (or one of them) willbe referred to as AI driving.

First, for ease of explanation, it is assumed that an IC chip 14 of thepresent invention is compatible with 64-gradation display. To implementAI driving, it is desirable to extend a range of gradationrepresentation. For ease of explanation, it is assumed that a sourcedriver circuit (IC) 14 of the present invention is compatible with64-gradation display and that image data consists of 256 gradations. Theimage data is gamma-converted to suit the gamma characteristics of theEL display apparatus. The gamma conversion expands 256 gradations into1024 gradations. The gamma-converted image data goes through an errordiffusion process or frame rate control (FRC) process to be compatiblewith the 64-gradation source data and then it is applied to the sourcedriver circuit 14.

The FRC achieves high-gradation display by superimposing image displayon a frame-by-frame basis. As illustrated in FIG. 99, the errordiffusion process scatters, for example image data of pixel A by 7/16 tothe right, 3/16 to the lower left, 5/16 to the bottom, and 1/16 to thelower right with respect to a processing direction. The diffusionprocess achieves high-gradation display. This is a kind of areagradation.

For ease of illustration, it is assumed in FIGS. 80 and 81 that64-gradation display is converted into 512-gradation display. The errordiffusion processing or frame rate control (FRC) is used for theconversion. However, the process in FIG. 80, may be interpreted as imagebrightness conversion rather than gradation conversion.

FIG. 80 illustrates an image conversion process based on the drivemethod according to the present invention. The horizontal axis in FIG.80 represents gradation (number). The larger the gradation (number), thebrighter the screen is. Conversely, the smaller the gradation (number),the darker the image is. The vertical axis represents frequency. Thefrequency represents a histogram of brightness of the pixels composingan image. For example, A1 in FIG. 80(a) shows that pixels with abrightness corresponding to the 24th gradation level occur mostfrequently in the image.

FIG. 80(a) shows an example in which display brightness is changed whilemaintaining the number of gradations. Suppose, A1 is an original image.The original image is expressed in approximately 64 gradations. A2 is anexample in which the center of brightness is moved to the 256thgradation while maintaining the number of gradations. A3 is an examplein which the center of brightness is moved to the 448th gradation whilemaintaining the number of gradations. Such conversion can be performedby adding data of a predetermined size to the image data.

However, the gradation conversion in FIG. 80(a) is difficult for thedrive method according to the present invention to implement. The drivemethod according to the present invention performs gradation conversionshown in FIG. 80(b).

FIG. 80(b) is an enlargement of frequency distribution of the originalimage. Suppose, B1 is an original image. The original image is expressedin approximately 64 gradations. B2 is an example in which the originalimage is expressed in 256 gradations. The screen becomes brighter andthe range of gradations is expanded. B3 is an example in which the rangeof gradations is further expanded to 512 gradations. The screen displaybecomes still brighter and the range of gradations is expanded.

The drive method according to the present invention can easily implementthe gradation conversion in FIG. 80(b) by varying the reference currentdescribed with reference to FIG. 77, by varying (controlling) the dutyratio in FIG. 78, or by the combination of the methods in FIGS. 77 and78. Image brightness can be controlled easily by reference currentcontrol or duty cycle control. For example, if the display conditionrepresented by B2 in FIG. 80(b) exists when the duty ratio is 1/4, thedisplay condition represented by B1 in FIG. 80(b) takes place when theduty ratio is changed to 1/16. If the duty ratio is changed to 1/2, thedisplay condition represented by B3 in FIG. 80(b) takes place. The sameapplies to the reference current control. By doubling the magnitude ofreference current or reducing it to a quarter, it is possible to createimage display shown in FIG. 80(b) The horizontal axis in FIG. 80(b)represents the number of gradations. The drive method according to thepresent invention does not increase the number of gradations. The drivemethod according to the present invention is characterized in that thenumber of gradations is maintained even if brightness changes.Specifically, the 64th gradation in B1 of FIG. 80(b) is converted intothe 256th gradation in B2. However, the number of gradations in B2 is64. The gradation range is extended to four times that of B1. Theconversion from B1 to B2 is no other than dynamic conversion of imagedisplay. This is equivalent to implementation of high-gradation display.Thus, this makes it possible to achieve high-quality display.

Similarly, the 64th gradation in B1 of FIG. 80(b) is converted into the512th gradation in B3. However, the number of gradations in B3 is 64.The gradation range is extended to eight times that of B1. Theconversion from B1 to B3 is no other than dynamic conversion of imagedisplay.

The method in FIG. 80(a) can improve the brightness of the screen 50.However, the entire screen becomes whitish. There are relatively smallincreases in current consumption (though current consumption increasesin proportion to screen brightness). The method in FIG. 80(b) canimprove the brightness of the screen 50 and increase a display range ofgradations. Consequently, there is no degradation in image quality.However, current consumption increases greatly.

Assuming that the number of gradations is proportional to screenbrightness and that the original image is expressed in 64 gradations,then “increase in the number of gradations (expansion of the dynamicrange)”=“increase in brightness.” Thus, power consumption (currentconsumption) increases. To solve this problem, the present inventionuses the reference current control system in FIG. 77, the duty cyclecontrol system in FIG. 78, or a combination thereof.

If image data of one screen is generally large, the sum total of imagedata is large as well. Take as an example a white raster in 64-gradationdisplay, since the white raster as image data is represented by 63, thesum total of image data is given by “the pixel count of the screen50”×63. In the case of white display with the maximum brightness in1/100 of the screen, the sum total of image data is given by “the pixelcount of the screen 50”×1/100×63.

The present invention determines the sum total of image data or a valuewhich allows the current consumption of the screen to be estimated, andperforms duty cycle control or reference current control using the sumtotal or the value.

Incidentally, although the sum total of image data is determined above,this is not restrictive. For example, an average level of one frame ofimage data may be determined and used. In the case of an analog signal,the average level can be determined by filtering the analog image signalwith a capacitor. Alternatively, it is possible to extract a directcurrent level from the analog image signal through a filter, subject thedirect current level to A/D conversion, and use the result as the sumtotal of image data. In this case the image data may be referred to asan APL level.

Also, there is no need to add all the data composing an image on thescreen 50. It is possible to pick up 1/W (w is larger than 1) of data onthe screen 50 and determine the sum total of the data picked up.

For ease of explanation, it is assumed in the above case that the sumtotal of image data is determined. Calculation of the sum total of imagedata is often tantamount to determining the APL level of the image.Also, means of adding the sum total of image data digitally isavailable, and the above-mentioned methods of determining the sum totalof image in a digital or analog fashion will be referred to as an APLlevel hereinafter for ease of explanation.

In the case of a white raster, since an image consists of 6 bits each ofR, G, and B, the APL level is given by 63× pixel count (where 63represents the data, which corresponds to the 63rd gradation, and thepixel count of a QCIF panel is 176×RGB×220). Thus, the APL level reachesits maximum. However, since the current consumption of the EL elements15 vary among R, G, and B, preferably the image data should becalculated separately for R, G, and B.

To solve the above problem, an arithmetic circuit shown in FIG. 84 isused. In FIG. 84, reference numerals 841 and 842 denote multipliers, ofwhich 841 is a multiplier used to weight emission brightness. Luminosityvaries among R, G, and B. The ratio of NTSC-based luminosity among R, G,and B is R:G:B=3:6:1. Thus, the multiplier 841R for R multiplies R imagedata (Rdata) by 3, multiplier 841G for G multiplies G image data (Gdata)by 6, and multiplier 841B for B multiplies B image data (Bdata) by 1.

The light emission efficiency of the EL elements 15 varies among R, G,and B. The light emission efficiency of B is the lowest. The lightemission efficiency of G is the next lowest. The light emissionefficiency of R is good. Thus, the multipliers 842 weight data by theluminous efficiencies. The multiplier 842R for R multiplies the R imagedata (Rdata) by the light emission efficiency of R, multiplier 842G forG multiplies the G image data (Gdata) by the light emission efficiencyof G, and multiplier 842B for B multiplies the B image data (Bdata) bythe light emission efficiency of B.

The results produced by the multipliers 841 and 842 are added by anadder 843 and stored in a summation circuit 844. Then, the referencecurrent control in FIG. 77 and duty cycle control in FIG. 78 areperformed based on the results produced by the summation circuit 87.

The method in FIG. 84 allows a luminance signal (Y signal) to besubjected to duty cycle control and reference current control. However,duty control based on detection of the luminance signal (Y signal) mayinvolve problems. For example, a blue back screen is a case in point.For a blue back screen, the EL panel consumes relatively large current.However, display brightness is low because of low luminosity of blue(B). Consequently, the sum total (APL level) of the luminance signal (Ysignal) is calculated to be smaller, resulting in a high duty ratio.This causes flickering and the like.

To deal with this problem, it is recommendable to use the multipliers841 in a pass-through mode. This makes it possible to find the sum total(APL level) based on current consumption. It is desirable to determineboth the sum total (APL level) based on the luminance signal (Y signal)and sum total (APL level) based on current consumption and find aconsolidated APL level taking both of them into consideration. Then, theduty cycle control and reference current control should be performedbased on the consolidated APL level.

A black raster corresponds to the 0th gradation in the case of64-gradation display, and thus the minimum APL level is 0. In drivemethods in FIG. 80, power consumption (current consumption) isproportional to image data. Regarding image data, there is no need tocount all the bits in the data on the screen 50. For example, if animage consists of 6-bit data, only the most significant bit (MSB) may becounted. In this case, 33 gradations are counted as 1. Thus, the APLlevel varies with the image data on the screen 50.

According to the present invention, either the duty cycle control inFIG. 78 or reference current control in FIG. 77 is performed dependingon the APL level obtained.

For ease of understanding, description will be given citing concretefigures. However, this is virtual. In actual practice, control data andcontrol directions must be determined through experiments and imageevaluations.

Let us assume that the maximum current that can flow through an EL panelis 100 mA, that the sum total (APL level) in white raster display is 200(no unit), and that a current of 200 mA will flow through the EL panelif the APL level of 200 is applied directly to the panel. Incidentally,when the APL level is 0, a zero (0 mA) current flows through the ELpanel. Also, it is assumed that when the APL level is 100, the dutyratio is 1/2.

Thus, when the APL level is 100 or above, it is necessary to limit thecurrent to 100 mA or below. The simplest way is to set the duty ratio to1/2×1/2=1/4 when the APL level is 200 and set the duty ratio to 1/2 whenthe APL level is 100. When the APL level is between 100 and 200, theduty ratio should be controlled so as to fall within a range of 1/4 to1/2. The duty ratio can be kept between 1/4 and 1/2 by controlling thenumber of gate signal lines 17 b selected simultaneously by theEL-selection-side gate driver circuit 12 b.

However, if duty cycle control is performed considering only the APLlevel, the average brightness (APL) of the screen 50 will vary with theimage, causing flicker. To solve this problem, the APL level is retainedfor a period of at least 2 frames, preferably 10 frames, or morepreferably 60 frames, and the duty ratio for duty cycle control iscalculated using the data retained for this period. Also, it ispreferable to extract characteristics of the screen 50 including itsmaximum brightness (MAX), minimum brightness (MIN), and brightnessdistribution (SGM) for use in the duty cycle control. Needless to say,the above items are also applicable to reference current control.

Also, it is important to do black stretching and white stretching basedon the extracted image characteristics. Preferably, this is done takinginto consideration the maximum brightness (MAX), minimum brightness(MIN), and brightness distribution (SGM). For example, in FIG. 81(a),central part Kb of the image data is distributed around the 256thgradation, high-brightness part Kc is distributed around the 320thgradation, and low-brightness part Ka is distributed around the 128thgradation.

FIG. 81(b) shows an example in which the image in FIG. 81(a) hasundergone black stretching and white stretching. However, there is noneed to perform both black stretching and white stretching at the sametime. Only one of them will be sufficient. Also, the central part of theimage (Kb in FIG. 81(a)) may be moved to the low-brightness part Ka orhigh-brightness part Kc. Information about such proper movements canalso be obtained from the APL level, maximum brightness (MAX), minimumbrightness (MIN), and brightness distribution (SGM). However, someinformation is obtained empirically because it is affected by humanvisibility. Thus, studies should be conducted through repeatedexperiments and image evaluations. However, image processing such asblack stretching or white stretching can be performed easily becausegamma curves can be determined based on computations or lookup tables.The processes in FIG. 81(b) enhance contrast, and thus help achieveproper image display.

Incidentally, the brightness of the screen 50 is varied by duty cyclecontrol in the manner shown in FIG. 82. A drive method in FIG. 82(a)involves changing the display area 53 continuously. The screen 50 inFIG. 82(a 1) is brighter than the screen 50 in FIG. 82 (a 2). The screen50 in FIG. 82(an) is the brightest. The drive method based on duty cyclecontrol in FIG. 82(a) is suitable for movie display.

FIG. 82(b) shows a drive method which drives the display area 53 bydividing it. In FIG. 82(b 1), two display areas 53 are generated atdifferent locations on the screen 50. In FIG. 82(b 2), two display areas53 are generated at different locations on the screen 50 as in the caseof FIG. 82(b 1) but a pixel row has been added to one of the two displayareas 53 (one of the display areas 53 contains one pixel row and theother contains two pixel rows). In FIG. 82(b 3), two display areas 53are generated at different locations on the screen 50 as in the case ofFIG. 82(b 2), but a pixel row has been added to one of the two displayareas 53 (both display areas 53 contain two pixel rows). In this way,duty cycle control may be performed by scattering display areas 53.Generally, the drive method in FIG. 82(b) is suitable for still picturedisplay.

In FIG. 82(b), display areas 53 are scattered to two locations for easeof drawing. Actually, display areas 53 are scattered to three or morelocations.

FIG. 83 is a block diagram of a drive circuit according to the presentinvention. The drive circuit according to the present invention will bedescribed below. The drive circuit in FIG. 83 is configured to receiveinput of a Y/UV video signal and composite (COMP) video signal. Of thetwo signals, the one to be input is selected by a switch circuit 831.

The video signal selected by the switch circuit 831 is subjected todecoding and A/D conversion by a decoder and A/D converter, and therebyconverted into digital RGB image data. Each of the R, G, and B imagedata is 8-bit data. Also, the RGB image data go through gamma processingin a gamma circuit 834. At the same time, a luminance (Y) signal isdetermined. As a result of the gamma processing, each of the R, G, and Bimage data is converted into 10-bit data.

After the gamma processing, the image data are subjected to an FRCprocess or error diffusion process by a processing circuit 835. The RGBimage data are converted into 6-bit data by the FRC process or errordiffusion process. Then, the image data are subjected to an AI processof peak current process by an AI processing circuit 836. Also, moviedetection is carried out by a movie detection circuit 837. At the sametime, color management process is performed by a color managementcircuit 838.

Results of the processes performed by the AI processing circuit 836,movie detection circuit 837, and color management circuit 838 are sentto an arithmetic circuit 839 and converted by the arithmetic circuit 839into data for use in control operations, duty cycle control, andreference current control. The resulting data are sent to the sourcedriver circuit 14 and gate driver circuit 12 as control data.

The data for use in duty cycle control is sent to the gate drivercircuit 12 b, which performs duty cycle control. On the other hand, thedata for use in duty cycle control is sent to the source driver circuit14, which performs reference current control. The image data subjectedto the gamma correction as well as to the FRC or error diffusion processare also sent to the source driver circuit 14.

The image data conversion in FIG. 81(b) should be performed by way of agamma process in the gamma circuit 834. The gamma circuit 834 performsgradation conversion using multi-point polygonal gamma curves.256-gradation image data are converted into 1024-gradation image datausing multi-point polygonal gamma curves.

Although it has been stated that the gamma circuit 834 performs a gammaprocess using multi-point polygonal gamma curves, this is notrestrictive. Single-point polygonal gamma curves may be used for thegamma correction as shown in FIG. 85. Since hardware needed to generatesingle-point polygonal gamma curves is small in scale, costs of controlICs can be reduced.

Referring to FIG. 85, curve a represents polygonal gamma conversion inthe 32nd gradation, curve b represents polygonal gamma conversion in the64th gradation, curve c represents polygonal gamma conversion in the96th gradation, and curve d represents polygonal gamma conversion in the128th gradation. If image data are concentrated in high gradations,gamma curve d in FIG. 85 should be selected to increase the number ofhigh gradations. If image data are concentrated in low gradations, gammacurve a in FIG. 85 should be selected to increase the number of lowgradations. If image data are scattered, gamma curve b or c in FIG. 85should be selected. Incidentally, although it has been stated in theabove example that a gamma curve is selected, actually the gamma curveis generated by arithmetic operations rather than being selected.

Gamma curves are selected by taking into consideration the APL level,maximum brightness (MAX), minimum brightness (MIN), and brightnessdistribution (SGM). Also, duty cycle control and reference currentcontrol should be taken into consideration.

FIG. 86 shows an example of multi-point polygonal gamma curves. If imagedata are concentrated in high gradations, gamma curve n in FIG. 85should be selected to increase the number of high gradations. If imagedata are concentrated in low gradations, gamma curve a in FIG. 85 shouldbe selected to increase the number of low gradations. If image data arescattered, gamma curves b to n−1 in FIG. 85 should be selected. Gammacurves are selected by taking into consideration the APL level, maximumbrightness (MAX), minimum brightness (MIN), and brightness distribution(SGM). Also, duty cycle control and reference current control should betaken into consideration.

It is also useful to vary gamma curves according to environment in whichthe display panel (display apparatus) is used. EL display panels, inparticular, achieve proper image display, but do not provide visibilityin low gradation part when used outdoors. This is because the EL displaypanels are self-luminous. So gamma curves may be varied as shown in FIG.87. Gamma curve a is for indoor use while gamma curve b is for outdooruse. To switch between gamma curves a and b, the user operates a switch.Also, the gamma curves may be switched automatically by a photosensorwhich detects the brightness of extraneous light. Incidentally, althoughit has been stated that a gamma curves are switched, this is notrestrictive. Needless to say, a gamma curve may be generated bycalculation. In outdoor use, low gradation display part is not visiblebecause of bright extraneous light. Thus, it is useful to select gammacurve b which suppresses the low gradation display part.

In outdoor use, it is useful to generate gamma curves in the mannershown in FIG. 88. Output gradation of gamma curve a is set to 0 up tothe 128th gradation. Gamma conversion is carried out beginning with the128th gradation. In this way, by performing gamma conversion so as notto display low gradation part at all, it is possible to reduce powerconsumption. Also, gamma conversion may be performed in the mannerindicated by gamma curve b in FIG. 88. Output gradation of the gammacurve in FIG. 88 is set to 0 up to the 128th gradation. Then, beginningwith the 128th gradation, output gradation is set to 512 or higher.Gamma curve b in FIG. 88 displays high gradation part, reduces thenumber of output gradations, and thereby makes image display easy toview.

The drive method according to the present invention uses duty cyclecontrol and reference current control to control image brightness andextend a dynamic range. Also, it achieves high-current display.

In liquid crystal display panels, white display and black display aredetermined by transmission of a backlight. Even if a non-display area 52is generated on the screen 50 as in the case of the duty ratio drivingaccording to the present invention, transmittance during black displayis constant. Conversely, when a non-display area 52 is generated, whitedisplay brightness during one frame period lowers, resulting in reduceddisplay contrast.

In EL display panels, zero (0) current flows through the EL elements 15during black display. Thus, even if a non-display area 52 is generatedon the screen 50 as in the case of the duty ratio driving according tothe present invention, transmittance during black display is 0. A largenon-display area 52 lowers white display brightness. However, since thebrightness of black display is 0, the contrast is infinite. Thus, theduty ratio driving is the most suitable drive method for EL displaypanels. The above items also apply to reference current control. Even ifthe magnitude of reference current is changed, the brightness of blackdisplay is 0. A large reference current increases white displaybrightness. The reference current control also achieves proper imagedisplay.

Duty cycle control maintains the number of gradations and white balanceover the entire range of gradations. Also, the duty cycle control allowsthe brightness of the screen 50 to be changed nearly ten-hold. Also, thechange has a linear relationship with the duty ratio, and thus can becontrolled easily. However, the duty cycle control is N-pulse driving,which means that large currents flow through the EL elements 15. Sincelarge currents always flow through the EL elements regardless of thebrightness of the screen 50, the EL elements 15 are prone todegradation.

Reference current control increases the amounts of reference current toincrease screen brightness 50. Thus, large currents flow through the ELelements 15 only when the screen 50 is high. Consequently, the ELelements 15 are less prone to degradation. A problem with the referencecurrent control is that it tends to be difficult to maintain whitebalance when the reference current is varied.

The present invention uses both reference current control and duty cyclecontrol. When the screen 50 is close to white raster display, displaybrightness and the like are controlled by varying the duty ratio withreference currents set to fixed values. When the screen 50 is close toblack raster display, display brightness and the like are controlled byvarying the reference currents with the duty ratio set to a fixed value.

The duty cycle control is performed when the ratio of total data to amaximum value is between 1/10 and 1/1, inclusive. More preferably, it isperformed when the ratio of total data to the maximum value is between1/100 and 1/1, inclusive. On the other hand, the reference currentvariation (output current variation of the unit transistor 484) isperformed when the ratio of total data to the maximum value is between1/10 and 1/1000, inclusive. More preferably, the reference currentcontrol is performed when the ratio of total data to the maximum valueis between 1/100 and 1/2000, inclusive. Preferably, the duty cyclecontrol and reference current control do not overlap. Incidentally, theydo not overlap in FIG. 89, where the magnification of reference currentis varied when the ratio of total data to the maximum value is 1/100 orless and the duty ratio is varied when the ratio of total data to themaximum value is 1/100 or more.

For ease of explanation, it is assumed here that the maximum value ofthe duty ratio is 1/1 while the minimum value is 1/8. It is assumed thatthe magnification of reference current is varied from 1 to 3 times. Thesum of data is the sum total of the data on the screen 50. The maximumvalue (of the sum of data) is the sum total of image data in whiteraster display. Needless to say, there is no need to use the duty ratioof 1/1. The duty ratio of 1/1 is cited here as the maximum value. Itgoes without saying that the drive method according to the presentinvention may set the maximum duty ratio to 210/220 or the like.Incidentally, 220 is cited as an example of the number of pixel rows ina QCIF+display panel.

Preferably, the maximum value of the duty ratio is 1/1 and the minimumvalue is no smaller than 1/16. More preferably, the minimum value is nosmaller than 1/10 to reduce flickering. Preferably, a variable range ofthe reference current is no larger than 4 times. More preferably, it isno larger than 2.5 times. Too large a magnification of the referencecurrent will make the reference current generator circuit looselinearity, causing deviations in the white balance.

The statement that the ratio of total data (the sum of data) to themaximum value is 1/100 means, for example, 1/100 of a white window. Inthe case of natural images, this means a state in which the sum of pixeldata used for image display is equivalent to 1/100 of a white rasterdisplay. Thus, one white luminescent spot in 100 pixels is also anexample in which the ratio of total data to the maximum value equals1/100.

Although it is described below that the maximum value is the sum ofimage data of a white raster, this is for ease of explanation. Themaximum value is produced by an addition process or APL process of imagedata. Thus, the ratio of total data to the maximum value is a ratio tothe maximum value of the image data of the image to be processed.

The sum of data may be calculated using either current consumption orbrightness. Addition of brightness (image data) will be cited here forease of explanation. Generally, addition of brightness (image data) iseasier to process and can reduce the scale of controller IC hardware.Also, this method is free of flickering caused by duty cycle control andcan provide a wide dynamic range.

FIG. 89 shows an example obtained as a result of the reference currentcontrol and duty cycle control according to the present invention. InFIG. 89, the magnification of reference current is varied up to 3 timeswhen the ratio of total data to the maximum value is 1/100 or less. Theduty ratio is varied from 1/1 to 1/8 when the ratio of total data to themaximum value is 1/100 or more. Thus, when the ratio of total data tothe maximum value is between 1/1 and 1/10000, the duty ratio is varied 8times and the reference current is varied 3 times for a total of 24-foldchanges (8×3=24). Since both reference current control and duty cyclecontrol vary screen brightness, a 24 times larger dynamic range isobtained.

When the ratio of total data to the maximum value is 1/1, the duty ratiois 1/8. Thus, the display brightness is 1/8 the maximum value. The valueof 1/1 equals 1, which means white raster display. That is, during whiteraster display, the display brightness is reduced to 1/8 the maximumvalue. An image display area 53 makes up 1/8 of the screen 50 while anon-display area 52 makes up 7/8 of the screen 50. In an image with theratio of total data to the maximum value being close to 1/1, most of thepixels 16 represent high gradations. In terms of a histogram, most ofthe data are distributed in a high gradation region. In this imagedisplay, the image is subject to blooming and lacks contrast. Thus,gamma curve n or similar curve in FIG. 86 is selected.

When the ratio of total data to the maximum value is 1/100, the dutyratio is 1/1. The entire screen 50 is occupied by a display area 53.Thus, N-pulse driving is not performed. The emission brightness of theEL elements 15 becomes the display brightness of the screen 50 directly.The screen presents almost black display with images displayed only insome part. An image display in which the ratio of total data to themaximum value is 1/100 is like a dark night sky in which the moon isout. In this display, if the duty ratio is changed to 1/1, the partwhich corresponds to the moon is displayed at 8 times the brightness ofa white raster. This makes it possible to achieve an image display witha wide dynamic range. Since only 1/100 of the area is used for imagedisplay, even if the brightness of this area is increased 8-fold, theincrease in power consumption is marginal.

In an image with the ratio of total data to the maximum value beingclose to 1/100, most of the pixels 16 represent low gradations. In termsof a histogram, most of the data are distributed in a low gradationregion. In this image display, the image is subject to loss of shadowdetail and lacks contrast. Thus, gamma curve b or similar curve in FIG.86 is selected.

Thus, the drive method according to the present invention increases themultiplier x of gamma with increases in the duty ratio, and decreasesthe multiplier x of gamma with decreases in the duty ratio.

In FIG. 89, when the ratio of total data to the maximum value is 1/100or less, the magnification of reference current is varied up to 3 times.When the ratio of total data to the maximum value is 1/100, the dutyratio is set to 1/1 to increase the screen brightness. As the ratio oftotal data to the maximum value gets smaller than 1/100, themagnification of reference current is increased. Thus, illuminatingpixels 16 emits light more brightly. For example, an image display inwhich the ratio of total data to the maximum value is 1/1000 is like adark night sky in which the stars are out. In this display, if the dutyratio is changed to 1/1, the parts which correspond to the stars aredisplayed at 16 (=8×2) times the brightness of a white raster. Thismakes it possible to achieve an image display with a wide dynamic range.Since only 1/1000 of the area is used for image display, even if thebrightness of this area is increased 16-fold, the increase in powerconsumption is marginal.

In reference current control, it is difficult to maintain white balance.However, in an image of the dark sky with the stars, even if the whitebalance is deviated, the deviation is not perceived visually. Thus, thepresent invention, which performs reference current control in a rangewhere the ratio of total data to the maximum value is very small,provides an appropriate drive method.

When the ratio of total data to the maximum value is 1/1000, the dutyratio is 1/1. The entire screen 50 is occupied by a display area 53.Thus, N-pulse driving is not performed. The emission brightness of theEL elements 15 becomes the display brightness of the screen 50 directly.The screen presents almost black display with images displayed only insome part.

In an image with the ratio of total data to the maximum value beingclose to 1/1000, most of the pixels 16 represent low gradations. Interms of a histogram, most of the data are distributed in a lowgradation region. In this image display, the image is subject to loss ofshadow detail and lacks contrast. Thus, gamma curve b or similar curvein FIG. 86 is selected.

Thus, the drive method according to the present invention increases themultiplier x of gamma with decreases in the reference current, anddecreases the multiplier x of gamma with increases in the referencecurrent.

In FIG. 89, changes in the reference current and duty ratio areillustrated linearly. However, the present invention is not limited tothis. As illustrated in FIG. 90, the magnification of reference currentand the duty ratio may be controlled curvilinearly. In FIGS. 89 and 90,since the ratio of total data to the maximum value in the horizontalaxis is logarithmic, it is natural that the graphs of reference currentcontrol and duty cycle control are curvilinear. Preferably, therelationship between the ratio of total data to the maximum value andmagnification of reference current as well as the relationship betweenthe ratio of total data to the maximum value and duty cycle control arespecified according to contents of image data, display condition ofimages, and external environment.

FIGS. 89 and 90 show examples in which common duty cycle control andreference current control are performed for R, G, and B. However, thepresent invention is not limited to this. The slope of change in themagnification of reference current may be varied among R, G, and B asillustrated in FIG. 91, in which the slope of change in themagnification of reference current for blue (B) is the largest, theslope of change in the magnification of reference current for green (G)is the next largest, and the slope of change in the magnification ofreference current for red (R) is the smallest. A large reference currentincreases the current flowing through the EL element 15. The lightemission efficiency of the EL elements 15 varies among R, G, and B. Alarge current flowing through the EL element lowers light emissionefficiency relative to applied current. This tendency is noticeableespecially in the case of B. Consequently, white balance is upset unlessthe amounts of reference current are adjusted among R, G, and B. Thus,as shown in FIG. 91, if the magnification of reference current isincreased (in an area where large currents flow through the EL elements15 of R, G, and B), it is useful to vary the magnification of referencecurrent among R, G, and B so that the white balance can be maintained.Preferably, the relationship between the ratio of total data to themaximum value and magnification of reference current as well as therelationship between the ratio of total data to the maximum value andduty cycle control are specified according to contents of image data,display condition of images, and external environment.

FIG. 91 has been an example in which the magnification of referencecurrent is varied among R, G, and B. In FIG. 92, duty cycle control isvaried as well. When the ratio of total data to the maximum value is1/100 or more, B and G have the same slope while R has a smaller slope.When the ratio of total data to the maximum value is 1/100 or less, Gand R have a duty ratio of 1/1 while B has a duty ratio of 1/2. Thisdrive method can be implemented using the drive methods described withreference to FIGS. 125 to 131. This drive method can optimize the RGBwhite balance. Preferably, the relationship between the ratio of totaldata to the maximum value and magnification of reference current as wellas the relationship between the ratio of total data to the maximum valueand duty cycle control are specified according to contents of imagedata, display condition of images, and external environment. Also, it ispreferable that they can be set or adjusted freely by the user.

In FIGS. 89 to 91, either the magnification of reference current or theduty ratio is varied depending on whether the ratio of total data to themaximum value is below or above 1/100, as an example. Either themagnification of reference current or the duty ratio is varied dependingon whether the ratio of total data to the maximum value takes a certainvalue so that the area in which the magnification of reference currentis varied and the area in which the duty ratio is varied will notoverlap. This makes it easy to maintain white balance. Specifically, theduty ratio is varied when the ratio of total data to the maximum valueis larger than 1/100 and the reference current is varied when the ratioof total data to the maximum value is smaller than 1/100 so that thearea in which the magnification of reference current is varied and thearea in which the duty ratio is varied will not overlap. This method ischaracteristic of the present invention.

Incidentally, although it has been stated that the duty ratio is variedwhen the ratio of total data to the maximum value is larger than 1/100and the reference current is varied when the ratio of total data to themaximum value is smaller than 1/100, the relationship may be reversed.That is, the duty ratio may be varied when the ratio of total data tothe maximum value is smaller than 1/100 and the reference current may bevaried when the ratio of total data to the maximum value is larger than1/100. Also, the duty ratio may be varied when the ratio of total datato the maximum value is larger than 1/10, the reference current may bevaried when the ratio of total data to the maximum value is smaller than1/100, and the magnification of reference current and the duty ratio maybe kept constant when the ratio of total data to the maximum value isbetween 1/100 and 1/10.

In some cases, the present invention is not limited to the abovemethods. As illustrated in FIG. 93, the duty ratio may be varied whenthe ratio of total data to the maximum value is larger than 1/100 andthe reference current for B may be varied when the ratio of total datato the maximum value is smaller than 1/10. Changes in the referencecurrent for B and changes in the duty ratio for R, G, and B areoverlapped.

If a bright screen and dark screen alternate quickly and the duty ratiois varied accordingly, flicker occurs. Thus, when the duty ratio ischanged from one value to another, preferably hysteresis (time delay) isprovided. For example, if a hysteresis period is 1 sec., even if thescreen changes its brightness a plurality of times within the period of1 sec., the previous duty ratio is maintained. That is, the duty ratiodoes not change.

The hysteresis time (time delay) is referred to as a Wait time. Also,the duty ratio before the change is referred to as a pre-change dutyratio and the duty ratio after the change is referred to as apost-change duty ratio.

If a small pre-change duty ratio changes its value, the change tends tocause flicker. A small pre-change duty ratio means a small sum of screen50 data or a large black display part on the screen 50. Maybe the screen50 presents intermediate gradations, resulting in high luminosity. Also,in an area with a small duty ratio, difference between pre-change andpost-change duty ratios tends to be large. Of course, if there is alarge difference of duty ratios, an OEV2 terminal should be used forcontrol. However, there is a limit to OEV2 control. In view of the abovecircumstances, the wait time should be increased when a pre-change dutyratio is small.

If a small pre-change duty ratio changes its value, the change is lessprone to cause flicker. A large pre-change duty ratio means a large sumof screen 50 data or a large white display part on the screen 50. Maybethe entire screen 50 presents a white display, resulting in lowluminosity. In view of the above circumstances, the wait time may beshort when a pre-change duty ratio is large.

The above relationship is shown in FIG. 94. The horizontal axisrepresents the pre-change duty ratio and the vertical axis representsthe Wait time (seconds). When the duty ratio is 1/16 or less, the Waittime is as long as 3 seconds. When the duty ratio is between 1/16 and8/16 (=1/2), the Wait time is varied between 3 seconds and 2 secondsdepending on the duty ratio. When the duty ratio is between 8/16 and16/16 (=1/1), the Wait time is varied between 2 seconds and 0 secondsdepending on the duty ratio.

In this way, the duty cycle control according to the present inventionvaries the Wait time with the duty ratio. When the duty ratio is small,the Wait time is increased and when the duty ratio is large, the Waittime is decreased. That is, in a drive method which varies at least theduty ratio, a first pre-change duty ratio is smaller than a secondpre-change duty ratio and the Wait time for the first pre-change dutyratio is set longer than the Wait time for the second pre-change dutyratio.

In the above example, the Wait time is controlled or prescribed based onthe pre-change duty ratio. However, there is only a small differencebetween pre-change duty ratio and post-change duty ratio. Thus, in theabove example, the term “pre-change duty ratio” may be replaced with theterm “post-change duty ratio.”

The above example has been described based on pre-change and post-changeduty ratios. Needless to say, the Wait time is increased when there is alarge difference between pre-change and post-change duty ratios. Also,it goes without saying that when there is a large duty ratio difference,an intermediate duty ratio should be provided between the pre-change andpost-change duty ratios.

The duty cycle control method according to the present inventionprovides a long Wait time when there is a large difference betweenpre-change and post-change duty ratios. That is, it varies the Wait timedepending on the difference between pre-change and post-change dutyratios. Also, it allows for a long Wait time when there is a large dutyratio difference.

Also, the duty ratio method according to the present invention providesan intermediate duty ratio before a post-change duty ratio when there isa large duty ratio difference.

In the example in FIG. 94, common Wait time is used for red (R), green(G), and blue (B). Needless to say, however, the present inventionallows the Wait time to be varied among R, G, and B. This is becauseluminosity varies among R, G, and B. By specifying the Wait timeaccording to luminosity, it is possible to achieve better image display.

The above example concerns duty cycle control. Preferably, Wait time isspecified in reference current control as well. FIG. 96 shows anexample.

A small reference current makes the screen 50 dark while a largereference current makes the screen 50 bright. In other words, a lowmagnification of reference current means an intermediate-gradationdisplay mode. When the magnification of reference current is high, thescreen 50 is in high-brightness mode. Thus, when the magnification ofreference current is low, the Wait time should be increased because ofhigh visibility of changes. On the other hand, when the magnification ofreference current is high, the Wait time may be decreased because of lowvisibility of changes. Thus, the Wait time can be specified in relationto the magnification of reference current as illustrated in FIG. 96.

The present invention calculates (detects) the sum of data or APL andperforms duty cycle control and reference current control based on theresulting values. FIG. 98 is a flowchart showing how the duty ratio andthe magnification of reference current are determined.

As illustrated in FIG. 98, an approximate APL (preliminary APL) iscalculated based on inputted image data. The value and magnification ofreference current are determined based on the APL. The determinedreference current and its magnification are converted into electronicregulation data and applied to the source driver circuit 14.

On the other hand, image data is fed into a gamma processing circuit,where gamma characteristics are determined. An APL is calculated fromthe image data whose gamma characteristics have been determined. A dutyratio is determined from the calculated APL. Then, a duty pattern isdetermined depending on whether the image is a moving picture or stillpicture. The duty pattern represents distribution of a non-display area52 and display area 53. In the case of a moving picture, an undividednon-display area 52 is inserted. In the case of a still picture, adivided non-display area 52 is inserted in a scattered manner. Thus, astill picture is converted into a distribution pattern which involvesinserting a divided non-display area 52 and display-non-display area 52in a scattered manner. A moving picture is converted into a distributionpattern which involves inserting an undivided non-display area 52. Theresulting distribution pattern is applied as a start pulse ST (see FIG.6) of the gate driver circuit 12 b.

With reference to FIGS. 94 and 95, description has been given of howWait time is controlled according to the duty ratio. With reference toFIGS. 89 to 93, description has been given of how duty cycle control isperformed according to the sum of data. FIG. 103 is a more detailedexplanatory diagram showing how to perform duty cycle control and Waittime. For ease of explanation, temporal factors and the like areexpressed in a reduced form.

In FIG. 103, the top row contains the frame (field) number. The secondrow contains the APL level (sum of data). The third row contains thecorresponding duty ratio calculated from the APL level. The bottom rowcontains the duty ratio (processed duty ratio) corrected for the Waittime. Thus, depending on the APL level of the frame, the correspondingduty ratio (in the third row) varies as follows:8/64→9/64→9/64→10/64→9/64→10/64→11/64→11/64→12/64→14/64.

In contrast to the corresponding duty ratio, the processed duty ratiovaries as follows, allowing for the Wait time:8/64→8/64→9/64→9/64→9/64→10/64→10/64→11/64→12/64→12/64→ . . .

In FIG. 103, the corresponding duty ratios are corrected for the Waittime. The numerators of the processed duty ratios are integers (cf. inFIG. 107, numerators contain a decimal point). In FIG. 103, the dutyratios are varied smoothly so that no flicker will occur. In frame 3, 4,and 5 in FIG. 103, the corresponding duty ratio changes to 9/64, 10/64,and 9/64, respectively. The processed duty ratios after Wait timecontrol are 9/64, 9/64, and 9/64 (a corrected value is indicated bydotted lines in frame 4). In frame 9, 10, and 11 in FIG. 103, thecorresponding duty ratio changes to 12/64, 14/64, and 11/64,respectively. The processed duty ratios after Wait time control are12/64, 12/64, and 11/64 (a corrected value is indicated by dotted linesin frame 10). In this way, hysteresis (a time delay or low-pass filter)is provided through Wait time control to prevent the duty ratio fromchanging even if the APL level changes sharply.

The duty cycle control described above does not need to complete in asingle frame or single field. Duty cycle control may be performed atintervals of a few fields (few frames) In that case, an average dutyratio over a few fields (few frames) is used. Incidentally, whenperforming duty cycle control at intervals of a few fields (few frames),preferably each interval should contain not more than 6 fields (6frames) A longer period may cause flicker. Also, the number of fields(frames) does not need to be an integer, and may be, for example, 2.5frames (2.5 fields). That is, the present invention is not limited to aspecific number of fields (frames) per period.

FIG. 104 shows an example in which duty cycle control is performed atintervals of a few fields (few frames). FIG. 104 shows a concept of howto perform duty cycle control at intervals of a few fields (few frames).M corresponds to a period in which duty cycle control is performed. Ifone field (frame) consists of 256 pixel rows, M=1024 corresponds to fourfields (four frames). That is, FIG. 104 shows an example in which dutycycle control is performed at intervals of four fields (four frames).

M indicates a data string retained in the shift register 61 b of thegate driver circuit 12 b (see FIG. 6). The retained data string containsdata as to whether to apply a turn-on voltage or turn-off voltage to thegate signal line 17 b. The average value of the retained data stringrepresents a duty ratio. Needless to say, in FIG. 104, M may be equal toN. Also, it goes without saying that in some cases, duty cycle controlmay be performed by satisfying M<N.

For example, in a retained data string M=1024, if a turn-on voltageconsists of 256 and a turn-off voltage consists of 768, the duty ratiois 256/1024=1/4. Incidentally, turn-on voltage data is retained in acluster when a still picture is displayed and retained in a scatteredmanner when a moving picture is displayed.

That is, turn-on and turn-off voltage data strings are applied virtuallyto the gate signal line 17 b of the EL display panel in sequence. Asturn-on and turn-off voltages are applied in sequence, the EL displaypanel is displayed at a predetermined brightness under duty cyclecontrol.

FIG. 105 is a block diagram showing a circuit configuration used toimplement the duty cycle control shown in FIG. 104. First, a videosignal (image data) is converted into a luminance signal by a Yconversion circuit 1051. Then, an APL level (the sum of data or ratio oftotal data to the maximum value) is determined by an APL arithmeticcircuit 1052. The duty ratio is calculated based on the APL level on afield-by-field (frame-by-frame) basis and results are stored in a stack1053. The stack circuit 1053 has a first-in-first-out configuration.Incidentally, the duty ratio is corrected by Wait time control andstored in the stack circuit 1053. The duty ratio data stored in thestack circuit 1053 is applied as a start pulse ST (see FIG. 6) of theshift register 61 b by a parallel/serial (P/S) conversion circuit 1054,and then turn-on and turn-off voltages of the gate signal line 17 b areoutput form the gate driver circuit 12 b according to the sequence ofthe applied data.

In the above example, duty cycle control is performed on afield-by-field basis or frame-by-frame basis. However, the presentinvention is not limited to this. For example, designating that 1frame=4 fields, duty cycle control may be performed in units of multiplefields. By performing duty cycle control using multiple fields, it ispossible to achieve smooth image display without flickering.

In FIG. 106, reference numeral 1-1 denotes the first field in the firstframe, 1-2 denotes the second field in the first frame, 1-3 denotes thethird field in the first frame, and 1-4 denotes the fourth field in thefirst frame. Reference numeral 2-1 denotes the first field in the secondframe.

To change the duty ratio from 128/1024 to 132/1024, it is changed to128/1024 in 1-1, 129/1024 in 1-2, 130/1024 in 1-3, 131/1024 in 1-4, and132/1024 in 2-1. This makes it possible to change from 128/1024 to132/1024 smoothly.

To change the duty ratio from 128/1024 to 130/1024, it is changed to128/1024 in 1-1, 128/1024 in 1-2, 129/1024 in 1-3, 129/1024 in 1-4, and130/1024 in 2-1. This makes it possible to change from 128/1024 to130/1024 smoothly.

To change the duty ratio from 128/1024 to 136/1024, it is changed to128/1024 in 1-1, 130/1024 in 1-2, 132/1024 in 1-3, 134/1024 in 1-4, and136/1024 in 2-1. This makes it possible to change from 128/1024 to136/1024 smoothly.

In field-based (frame-based) duty cycle control, the numerator of theduty ratio does not need to be an integer. For example, the numeratormay contain a decimal fraction as shown in FIG. 107. This can beaccomplished easily by controlling the OEV2 terminal. Also, the use of aduty ratio averaged over multiple frames (fields) will make denominatorscontain decimal fractions. Conversely, a decimal may be used as thedenominator of a duty ratio. In FIG. 107, the numerators are decimalssuch as 30.8 and 31.2. Incidentally, by using integers larger thancertain values for numerators and denominators, it is possible toeliminate the need for decimal fractions.

Duty ratio patterns are varied between moving pictures and stillpictures. If a duty ratio pattern is changed sharply, changes in theimage may be perceived. Also, flicker may occur. This problem is causedby difference between duty ratios of moving pictures and still pictures.Moving pictures employ a duty pattern which involves inserting anundivided non-display area 52. Still pictures employ a duty patternwhich involves inserting a divided non-display area 52 in a scatteredmanner. The surface ratio between non-display area 52 and screen area 50provides the duty ratio. However, even if the duty ratio is the same,human visibility varies with the distribution of non-display areas 52.It is believed that human responsiveness to moving pictures plays a rolehere.

An intermediate moving picture has a distribution pattern midway betweenthe distribution pattern of a moving picture and distribution pattern ofa still picture. A plurality of modes may be prepared for intermediatemoving pictures and one of a plurality of moving pictures may beselected according to a movie mode or still picture mode before change.The plurality of intermediate movie modes may include, for example, adistribution pattern close to that of movie display—such as adistribution pattern with a non-display area 52 divided into threeparts—or conversely, a distribution pattern in which a dividednon-display area is scattered widely as is the case with a stillpicture.

There are various still pictures: some are bright, others are dark. Thesame applies to moving pictures. Thus, the intermediate movie mode tochange over to may be determined according to the mode before thechange. In some cases, a change from a moving picture to a still picturemay occur directly without going through an intermediate moving picture.For example, on a dark screen 50, a change from a movie display to astill picture display can take place directly without a feeling ofstrangeness. On the other hand, display modes may be switched via aplurality of intermediate movie displays. For example, it is possible tochange from a duty ratio for a movie display, through a duty ratio foran intermediate movie display 1 and a duty ratio for an intermediatemovie display 2, and to a duty ratio for a still picture display.

In FIG. 108, a change from a movie display to a still picture displayoccurs by way of an intermediate movie mode. Also, a change from a stillpicture display to a movie display occurs by way of an intermediatemovie mode. Preferably a Wait time is provided in a change betweendifferent display modes.

FIG. 110 shows duty ratios and the number of divisions in movie display,still picture display, and intermediate movie display which change fromone to another. In FIG. 110, a movie/still picture level of 0 indicatesthat image display is at a movie level, level 1 indicates that imagedisplay is in semi-movie (intermediate movie) mode, and level 2indicates that image display is in still picture mode.

The number of divisions is the number of parts into which a non-displayarea 52 is divided. Number 1 indicates that an undivided non-displayarea 52 is inserted. Number 30 indicates that a non-display area 52 isinserted being divided into 30 parts. Similarly, number 50 indicatesthat a non-display area 52 is inserted being divided into 50 parts. Theduty ratio represents a reduction rate of white display brightness asdescribed earlier. For example, a duty ratio of 1/2 indicates abrightness 1/2 the maximum white brightness.

As illustrated in FIG. 110, a movie/still picture level changes by wayof an intermediate movie (semi-movie) mode in a change from a movingpicture to a still picture and in a change from a still picture to amoving picture.

Preferably, a Wait time is provided in a change from a moving picture toa still picture as shown in FIG. 111. It is recommended to determine theWait time according to the ratio of moving pictures. “The number ofdifferent data items” on the horizontal axis in FIG. 110 indicates theratio of moving pictures detected between a frame and the next frame. Inother words, the horizontal axis represents the ratio of pixels whichdiffer in image data between frames. Thus, the larger the value, thecloser to a movie display. In FIG. 110, the closer to a movie display,the longer the Wait time.

To further describe duty cycle control, the organic EL display panelaccording to the present invention will be described. FIG. 112 is ablock diagram of the power supply circuit according to the presentinvention. Reference numeral 1122 denotes a control circuit, whichcontrols the midpoint potential of resistances 1125 a and 1125 b andoutputs a gate signal of a transistor 1126. A power supply Vpc isapplied to the primary side of a transformer 1121 and primary current istransmitted to the secondary side under on/off control of the transistor1126. Reference numeral 1123 denotes a rectifying diode and 1124 denotesa smoothing capacitor.

The organic EL display panel has an EL element 15 formed (placed)between an anode Vdd and cathode Vk. It is supplied with an anode Vddvoltage and cathode Vk voltage from the power supply circuit in FIG.112. When the EL element does not emit light, a zero (0) current flowsbetween the anode and cathode. The duty cycle control according to thepresent invention applies turn-on and turn-off voltages to the gatesignal line 17 b per pixel row to control current for the EL element.The location of the gate signal line 17 b to which the turn-on andturn-off voltages are applied is scanned. FIG. 97 shows an example inwhich a non-display area 52 is divided into four parts. The non-displayareas 52 differ in size among FIG. 97(a), 97(b), 97(c), and 97(d).However, the non-display areas 52 are scanned (move) from top to bottomof the screen 50. Similarly, display areas 53 are also scanned from topto bottom of the screen 50. Current does not flow through the ELelements of the pixels 16 which correspond to the non-display areas 52.On the other hand, current flows through the EL elements 15 whichcorrespond to the display areas 53.

Now, to describe a problem, a display pattern in which a non-displayarea 52 and display area 53 alternate every pixel row will beillustrated. This display mode is characterized by black and whitehorizontal stripes. Specifically, odd-numbered rows present whitedisplay while even-numbered rows present black display. This displaypattern is referred to as horizontal stripe display.

Assuming that there are 220 pixel rows, description will be given of aprocess which takes place when the duty ratio is 110/220. The duty ratioof 110/220 means a condition in which a turn-on voltage and turn-offvoltage are applied to gate signal lines 17 b every other pixel row. Thelocation of the gate signal line 17 b to which a turn-on voltage orturn-off voltage is applied is scanned in sync with a horizontalsynchronization signal. Thus, looking at the gate signal line 17 b of aspecific pixel row, a turn-on voltage and turn-off voltage are appliedto the gate signal line 17 b alternately in sync with a horizontalsynchronization signal. Looking at the entire screen 50, a turn-onvoltage is applied to even-numbered pixel rows. During this period, aturn-off voltage is applied to the odd-numbered pixel rows. After onehorizontal scanning period, a turn-on voltage is applied to theodd-numbered pixel rows. During this period, a turn-off voltage isapplied to the even-numbered pixel rows.

When odd-numbered pixel rows present white display and even-numberedpixel rows present horizontal stripe display, if a turn-on voltage isapplied to the odd-numbered pixel rows, current flows to the displayarea from the power supply circuit. However, if a turn-on voltage isapplied to the even-numbered pixel rows, current does not flow to thedisplay area from the power supply circuit because the even-numberedpixel rows are in black display mode. Thus, the power supply circuitdelivers and stops delivering current every other horizontal scanningperiod. This operation is not desirable for the power supply circuitbecause a transient phenomenon will occur in the power supply circuitand power supply efficiency will be lowered.

A drive method which solves the above problem is shown in FIG. 100.Instead of using a single duty ratio of 1/2, this method uses aplurality of duty ratios to drive the screen 50 so that current willflow constantly even in horizontal stripe display.

In FIGS. 100(a) and 100(b), duty ratios 1/2, 1/1, and 1/3 are used toachieve a duty ratio of 1/2 as a whole (when averaged over one frameperiod). In this way, by combining a plurality of duty ratios during oneframe period, it is possible to avoid turning on and off output currentfrom the power supply circuit even in horizontal stripe display. Orderlypatterns such as horizontal stripes are displayed relatively frequently.In contrast, duty cycle control using a duty ratio pattern which makesnon-display areas 52 spaced equally tends to burden the power supplycircuit. Thus, it is preferable to use a plurality of duty ratiopatterns simultaneously to drive the screen 50. Also, instead of using asingle duty ratio pattern, it is preferable to obtain a predeterminedduty ratio when duty ratios are averaged over a single frame or a fewframes (fields).

Incidentally, it goes without saying that the duty ratio patterns inFIG. 100 are scanned from top to bottom of the screen 50 as illustratedin FIG. 97. Also, although it has been stated that the duty cyclecontrol according to the present invention moves the scanning locationevery pixel row in sync with a horizontal synchronization signal, thisis not restrictive. The scanning location may be moved every few pixelrow in sync with a horizontal synchronization signal. Also, the scandirection is not limited to the top-to-bottom direction of the screen50. For example, it is also possible to scan the first field from top tobottom of the screen 50, and the second field from bottom to top of thescreen 50.

The drive method in FIG. 100 applies a turn-on voltage and turn-offvoltage to the gate signal line 17 b of each of discrete pixel rows.However, the present invention is not limited to this. FIG. 101(a) showspixel rows driven by the method shown in FIG. 100. Similar screen 50brightness can be achieved using the duty ratio patterns shown in FIG.101(b), where a turn-on voltage or turn-off voltage is applied toconsecutive pixel rows.

A great variety of duty ratio patterns can achieve the same screen 50brightness. Some patterns contain a very large number of finely dividednon-display areas 52 as illustrated in FIG. 102(a), others contain asmall number of divided non-display areas 52 as illustrated in FIG.102(b). The patterns in FIGS. 102(a) and 102(b) have the same duty ratiowhen the fractions are reduced to their lowest terms. Thus, the screenshave the same brightness.

EL display panels have a problem of image burn-in due to degradation ofEL elements 15. Fixed patterns, in particular, tend to cause imageburn-in. The present invention is equipped with a sub-image display area50 b (sub-screen) to display fixed patterns. A display area 50 a (mainscreen) is a movie display area which displays television images and thelike.

In the organic EL display panel according to the present invention inFIG. 147, gate driver circuits 12 are shared by the sub-screen 50 b andmain screen 50 a. It is assumed that the sub-screen 50 a has 20 pixelrows or more. Thus, the screen 50 consists, for example, of 220 pixelrows of the main screen 50 a and 24 pixel rows of the sub-screen 50 b.Incidentally, the number of pixel rows is 176 each for R, G, and B.

The main screen 50 a and sub-screen 50 b may be separated distinctly asillustrated in FIG. 149. In the figure, a space BL is provided betweenthe main screen 50 a and sub-screen 50 b. The space BL is an area whereno pixel 16 is formed.

W/L (W is the channel width of the driver transistors and L is thechannel length of the driver transistors) of the driver transistors 17 afor the pixels in the main screen (main panel) and sub-screen(sub-panel) may be varied. Basically, W/L of the sub-screen (sub-panel)should be increased. Also, the size of pixels 16 a in the main screen(main panel) 50 a and the size of pixels 16 b in the sub-screen(sub-panel) 50 b may be varied. Also, the anode voltage Vdd or cathodevoltage Vk applied to the sub-screen (sub-panel) 50 b may be differentfrom the anode or cathode power supply of the main screen (main panel)50 a.

When a sub-panel 71 a and main panel 71 a are superimposed asillustrated in FIG. 150(b), a cushioning sheet 1504 should be placed orformed between an encapsulation substrate 85 a (encapsulation layer) andencapsulation substrate 85 b (encapsulation layer). The cushioning sheet1504 may be a plate or sheet made of metal such as a magnesium alloy ora plate or sheet made of resin such as polyester.

As also illustrated in FIG. 150, the sub-panel 71 b may be providedseparately to present the sub-screen 50 b. A flexible board 84 isprovided between the main panel 71 a and sub-panel 71 b to connectsource signal lines 18 a and 18 b with each other. Connection wiring1503 is formed in advance on the flexible board 84. At a termination ofthe signal line 18 a is a analog switch group consisting of analogswitches 1501. The analog switches 1501 control whether a current signalfrom a source driver circuit 14 is supplied to the sub-panel 71 b.

A switch control wire 1502 is formed for on/off control of the analogswitches 1501. Logic signals fed to the switch control wire 1502 controlsignal supply to the sub-panel, and consequently images are displayed.

Incidentally, instead of forming gate driver circuits or mounting gatedriver IC chips in the sub-panel 71 b, gate signal lines 17 may beformed on the WR side as described with reference to FIG. 9 and theillumination control lines 401 described with reference to FIG. 40 maybe formed or placed.

Preferably, the analog switches 1501 are a CMOS type consisting of acombination of P-channel and N-channel transistors as described in FIG.152. An inverter 1521 is placed on the switch control wire 1502 to turnon and off the analog switches 1501. Analog switches 1501 b may beconstituted of only P-channel transistors, as illustrated in FIG. 153.

A configuration shown in FIG. 154 may be used if the sub-panel 71 b andmain panel 71 a differ in the number of source signal lines 18. Outputsof analog switches 1501 a and 1501 b are short-circuited and connectedto the same terminal 1322 a. Also, as illustrated in FIG. 155, theoutput of the analog switches 1501 b may be connected to the voltage Vddto prevent them from turning on. Besides, as illustrated in FIG. 156,analog switches 1501 a (1501 a 1 and 1501 a 2) may be placed or formedat terminations of source signal lines 18 which do not need to beconnected to the sub-panel 71 b. A turn-off voltage is applied to theanalog switches 1501 a to prevent them from turning on.

Next, description will be given of examples of display devices accordingto the present invention which run the drive systems according to thepresent invention. FIG. 157 is a plan view of a cell phone which is anexample of an information terminal. An antenna 1571, numeric keys 1572,etc. are mounted on a casing 1573. Reference numerals 1572 and the likedenote a display color switch key, power key, and frame rate switch key.

The key 1572 may be configured to switch among color modes as follows:pressing it once enters 8-color display mode, pressing it again enters4096-color display mode, and pressing it again enters 260,000-colordisplay mode. The key is a toggle switch which switch among colordisplay modes each time it is pressed. Incidentally, a display colorchange key may be provided separately. In that case, three (or more)keys 1572 are needed.

In addition to a push switch, the key 1572 may be a slide switch orother mechanical switch. Speech recognition may also be used forswitching. For example, the switch may be configured such that displaycolors on the display screen 50 of the display panel will change as theuser speaks a phrase such as “high-definition display,” “4096-colormode,” or “low-color display mode” into the phone. This can beimplemented easily using existing speech recognition technology.

Also, display colors may be switched electrically. It is also possibleto employ a touch panel which allows the user to make a selection bytouching a menu presented on the display part 50 of the display panel.Besides, display colors may be switched based on the number of times theswitch is pressed or based on a rotation or direction as is the casewith a click ball.

A key which changes frame rate or a key which switches between movingpictures and still pictures many be used in place of the display colorswitch key 1572. A key may switch two or more items at the same time:for example, among frame rates and between moving pictures and stillpictures. Also, the key may be configured to change the frame rategradually (continuously) when pressed and held. For that, among acapacitor C and a resistor R of an oscillator, the resistor R can bemade variable or replaced with an electronic regulator. Alternatively, atrimmer capacitor may be used as a capacitor C of the oscillator. Such akey can also be implemented by forming a plurality of capacitors in asemiconductor chip, selecting one or more capacitors, and connecting thecapacitors in parallel.

Furthermore, embodiments which use the EL display panel, EL displayapparatus, or drive method according to the present invention will bedescribed with reference to drawings.

FIG. 158 is a sectional view of a viewfinder according to an embodimentof the present invention. It is illustrated schematically for ease ofexplanation. Besides, some parts are enlarged, reduced, or omitted. Forexample, an eyepiece cover is omitted in FIG. 158. The above items alsoapply to other drawings.

Inner surfaces of a body 1573 are dark- or black-colored. This is toprevent stray light emitted from an EL display panel (EL displayapparatus) 1574 from being reflected diffusely inside the body 1573 andlowering display contrast. A phase plate (λ/4) 108, polarizing plate109, and the like are placed on an exit side of the display panel. Thishas also been described with reference to FIGS. 10 and 11.

An eye ring 1581 is fitted with a magnifying lens 1582. The observerfocuses on a display image 50 on the display panel 1574 by adjusting theposition of the eye ring 1581 in the body 1573.

If a convex lens 1583 is placed on the exit side of the display panel1574 as required, principal rays entering the magnifying lens 1582 canbe made to converge. This makes it possible to reduce the diameter ofthe magnifying lens 1582, and thus reduce the size of the viewfinder.

FIG. 159 is a perspective view of a video camera. A video camera has ataking (imaging) lens 1592 and a video camera body 1573. The taking lens1592 and view finder 1573 are mounted back to back with each other. Theviewfinder 1573 (see also FIG. 158) is equipped with an eyepiece cover.The observer views the image 50 on the display panel 1574 through theeyepiece cover.

The EL display panel according to the present invention is also used asa display monitor. The display screen 50 can pivot freely on a point ofsupport 1591. The display screen 50 is stored in a storage compartment1593 when not in use.

A switch 1594 is a changeover switch or control switch and performs thefollowing functions. The switch 1594 is a display mode changeoverswitch. The switch 1594 is also suitable for cell phones and the like.Now the display mode changeover switch 1594 will be described.

The drive methods according to the present invention include the onethat passes an N times larger current through EL elements 15 toilluminate them for a period equal to 1/M of 1F. By varying thisillumination period, it is possible to change brightness digitally. Forexample, designating that N=4, a four times larger current is passedthrough the EL elements 15. If the illumination period is 1/M, byswitching M among 1, 2, 3, and 4, it is possible to vary brightness from1 to 4 times. Incidentally, M may be switched among 1, 1.5, 2, 3, 4, 5,6, and so on.

The switching operation described above is used for cell phones,monitors, etc. which display the display screen 50 very brightly atpower-on and reduce display brightness after a certain period to savepower. It can also be used to allow the user to set a desiredbrightness. For example, the brightness of the screen is increasedgreatly outdoors. This is because the screen cannot be seen at alloutdoors due to bright surroundings. However, the EL elements 15deteriorate quickly under conditions of continuous display at highbrightness. Thus, the screen 50 is designed to return to normalbrightness in a short period of time if it is displayed very brightly. Abutton which can be pressed to increase display brightness should beprovided, in case the user wants to display the screen 50 at highbrightness again.

Thus, it is preferable that the user can change display brightness withthe button switch 1594, that the display brightness can be changedautomatically according to mode settings, or that the display brightnesscan be changed automatically by detecting the brightness of extraneouslight. Preferably, display brightness settings such as 50%, 60%, 80%,etc. are available to the user.

Preferably, the display screen 50 employs Gaussian display. That is, thecenter of the display screen 50 is bright and the perimeter isrelatively dark. Visually, if the center is bright, the display screen50 seems to be bright even if the perimeter is dark. According tosubjective evaluation, as long as the perimeter is at least 70% asbright as the center, there is not much difference. Even if thebrightness of the perimeter is reduced to 50%, there is almost noproblem. The self-luminous display panel according to the presentinvention generates a Gaussian distribution from top to bottom of thescreen using the N-fold pulse driving described above (a method whichpasses an N times larger current through EL elements 15 to illuminatethem for a period equal to 1/M of 1F).

Specifically, the value of M is increased in upper and lower parts ofthe screen and decreased in the center of the screen. This isaccomplished by modulating the operating speed of a shift register ofthe gate driver circuits 12. The brightness at the left and right of thescreen is modulated by multiplying video data by table data. By reducingperipheral brightness (at an angle of view of 0.9) to 50% through theabove operation, it is possible to reduce power consumption by 20%compared to brightness of 100%. By reducing peripheral brightness (at anangle of view of 0.9) to 70%, it is possible to reduce power consumptionby 15% compared to brightness of 100%.

Preferably a changeover switch is provided to enable and disable theGaussian display. This is because the perimeter of the screen cannot beseen at all outdoors if the Gaussian display is used. Thus, it ispreferable that the user can change display brightness with the buttonswitch, that the display brightness can be changed automaticallyaccording to mode settings, or that the display brightness can bechanged automatically by detecting the brightness of extraneous light.Preferably, display brightness settings such as 50%, 60%, 80%, etc. areavailable to the user.

Liquid crystal display panels generate a fixed Gaussian distributionusing a backlight. Thus, they cannot enable and disable the Gaussiandistribution. The capability to enable and disable Gaussian distributionis peculiar to self-luminous display devices.

A fixed frame rate may cause interference with illumination of an indoorfluorescent lamp or the like, resulting in flickering. Specifically, ifthe EL elements 15 operate on 60-Hz alternating current, a fluorescentlamp illuminating on 60-Hz alternating current may cause subtleinterference, making it look as if the screen were flickering slowly. Toavoid this situation, the frame rate can be changed. The presentinvention has a capability to change frame rates. Also, it allows thevalue of N or M to be changed in N-fold pulse driving (a method whichpasses an N times larger current through EL elements 15 to illuminatethem for a period equal to 1/M of 1F).

The above capabilities are implemented by way of the switch 1594. Theswitch 1594 switches among the above capabilities when pressed more thanonce, following a menu on the screen 50.

Incidentally, the above items are not limited to cell phones. Needlessto say, they are applicable to television sets, monitors, etc. Also, itis preferable to provide icons on the display screen to allow the userto know at a glance what display mode he/she is in. The above itemssimilarly apply to the following.

The EL display apparatus and the like according to this embodiment canbe applied not only to video cameras, but also to digital cameras suchas the one shown in FIG. 160, still cameras, etc. The display apparatusis used as a monitor 50 attached to a camera body 1601. The camera body1601 is equipped with a switch 1594 as well as a shutter 1603.

The display panel described above has a relatively small display area.However, with a display area of 30 inches or larger, the display screen50 tends to flex. To deal with this situation, the present inventionputs the display panel in a frame 1611 and attaches a fitting 1614 sothat the frame 1611 can be suspended as shown in FIG. 161. The displaypanel is mounted on a wall or the like using the fitting 1614.

A large screen size increases the weight of the display panel. As ameasure against this situation, the display panel is mounted on a stand1613, to which a plurality of legs 1612 are attached to support theweight of the display panel.

The legs 1612 can be moved from side to side as indicated by A. Also,they can be contracted as indicated by B. Thus, the display apparatuscan be installed even in a small space.

A television set in FIG. 161 has a surface of its screen covered with aprotective film (or a protective plate). One purpose of the protectivefilm is to prevent the surface of the display panel from breakage byprotecting from being hit by something. An AIR coat is formed on thesurface of the protective film. Also, the surface is embossed to reduceglare caused by extraneous light on the display panel.

A space is formed between the protective film and display panel byspraying beads or the like. Fine projections are formed on the rear faceof the protective film to maintain the space between the protective filmand display panel. The space prevents impacts from being transmittedfrom the protective film to the display panel.

Also, it is useful to inject an optical coupling agent into the spacebetween the protective film and display panel. The optical couplingagent may be a liquid such as alcohol or ethylene glycol, a gel such asacrylic resin, or a solid resin such as epoxy. The optical couplingagent can prevent interfacial reflection and function as a cushioningmaterial.

The protective film may be, for example, a polycarbonate film (plate),polypropylene film (plate), acrylic film (plate) polyester film (plate),PVA film (plate), etc. Besides, it goes without saying that anengineering resin film (ABS, etc.) may be used. Also, it may be made ofan inorganic material such as tempered glass. Instead of using aprotective film, the surface of the display panel may be coated withepoxy resin, phenolic resin, and acrylic resin 0.5 mm to 2.0 mm thick(both inclusive) to produce a similar effect. Also, it is useful toemboss surfaces of the resin.

It is also useful to coat surfaces of the protective film or coatingmaterial with fluorine. This will make it easy to wipe dirt from thesurfaces with a detergent. Also, the protective film may be made thickand used for a front light as well as for the screen surface.

The display panel according to the example of the present invention maybe used in combination with the three-side free configuration. Thethree-side free configuration is useful especially when pixels are builtusing amorphous silicon technology. Also, in the case of panels formedusing amorphous silicon technology, since it is difficult to controlvariations in the characteristics of transistor elements duringproduction processes, it is preferable to use the N-pulse driving, resetdriving, dummy pixel driving, or the like according to the presentinvention. That is, the transistors 11 according to the presentinvention are not limited to those produced by polysilicon technology,and they may be produced by amorphous silicon technology. Thus, thetransistors 11 composing the pixels 16 in the display panels accordingto the present invention may be formed by amorphous silicon technology.Needless to say the gate driver circuits 12 and source driver circuits14 may also be formed or constructed by amorphous silicon technology.

Incidentally, the N-fold pulse driving (FIGS. 13, 16, 19, 20, 22, 24,30, etc.) and the like according to the present invention are moreeffective for display panels which contain transistors 11 formed bylow-temperature polysilicon technology than display panels which containtransistors 11 formed by amorphous silicon technology. This is becauseadjacent transistors, when formed by amorphous silicon technology, havealmost equal characteristics. Thus, driving currents for individualtransistors are close to a target value even if the transistors aredriven by current obtained by addition (the N-fold pulse driving inFIGS. 22, 24, and 30, in particular, are effective for pixelconfigurations containing amorphous silicon transistors).

The duty cycle control driving, reference current control, N-fold pulsedriving, and other drive methods and drive circuits according to thepresent invention described herein are not limited to drive methods anddrive circuits for organic EL display panels. Needless to say they arealso applicable to other displays such as field emission displays (FEDS)as shown in FIG. 173.

In an FED shown in FIG. 173, an electron emission protuberance 1733(which corresponds to the pixel electrode 105 in FIG. 10) which emitselectrons in a matrix is formed on an array board 71. A pixel contains aholding circuit 1734 (which corresponds to the capacitor in FIG. 1)which holds image data received from a video signal circuit 1732 (whichcorresponds to the source driver circuit 14 in FIG. 1). Also, controlelectrodes 1731 are placed in front of the electron emissionprotuberance 1733. Voltage signals are applied to the control electrodes1731 by an on/off control circuit 1735 (which corresponds to the gatedriver circuit 12 in FIG. 1).

The pixel configuration in FIG. 173 can perform N-fold pulse driving,duty cycle control driving, etc. if a peripheral circuit shown in FIG.174 is added. An image data signal is applied to the source signal line18 from the video signal circuit 1732. A pixel 16 selection signal isapplied to a selection signal line 2173 by an on/off control circuit1735 a, and consequently pixels 16 are selected one after another andimage data is written into them. Also, an on/off signal is applied to anon/off signal line 1742 by an on/off control circuit 1735 b, andconsequently the FED of pixels is subjected to on/off control (dutycycle control).

The technical idea described in the example of the present invention canbe applied to video cameras, projectors, 3D television sets, projectiontelevision sets, etc. It can also be applied to viewfinders, cell phonemonitors, PHS, personal digital assistants and their monitors, anddigital cameras and their monitors.

Also, the technical idea is applicable to electrophotographic systems,head-mounted displays, direct view monitors, notebook personalcomputers, video cameras, electronic still cameras. Also, it isapplicable to ATM monitors, public phones, videophones, personalcomputers, and wristwatches and its displays.

Furthermore, it goes without saying that the technical idea can beapplied to display monitors of household appliances, pocket gamemachines and their monitors, backlights for display panels, orilluminating devices for home or commercial use. Preferably,illuminating devices are configured such that color temperature can bevaried. Color temperature can be changed by forming RGB pixels instripes or in dot matrix and adjusting currents passed through them.Also, the technical idea can be applied to display apparatus foradvertisements or posters, RGB traffic lights, alarm lights, etc.

Also, organic EL display panels are useful as light sources forscanners. An image is read with light directed to an object using an RGBdot matrix as a light source. Needless to say, the light may bemonochromatic. Besides, the matrix is not limited to an active matrixand may be a simple matrix. The use of adjustable color temperature willimprove imaging accuracy.

Also, organic EL display panels are useful as backlights of liquidcrystal display panels. Color temperature can be changed and brightnesscan be adjusted easily by forming RGB pixels of an EL display panel(backlight) in stripes or in dot matrix and adjusting currents passedthrough them. Besides, the organic EL display panel, which provides asurface light source, makes it easy to generate Gaussian distributionthat makes the center of the screen brighter and perimeter of the screendarker. Also, organic EL display panels are useful as backlights offield-sequential liquid crystal display panels which scan with R, G, andB lights in turns. Also, they can be used as backlights of liquidcrystal display panels for movie display by inserting black even if thebacklights are turned on and off.

Industrial Applicability

The source driver circuit of the present invention, in which transistorscomposing a current mirror are formed adjacent to each other, can reducevariations in output current caused by deviations in thresholds. Thus,it can reduce brightness irregularities of an EL display panel and hasgreat practical effect.

Also, the display panels, display apparatus, etc. of the presentinvention offer distinctive effects, including high quality, high moviedisplay performance, low power consumption, low costs, high brightness,etc., according to their respective configurations.

Incidentally, the present invention does not consume much power becauseit can provide power-saving information display apparatus. Also, it doesnot waste resources because it can reduce size and weight. Furthermore,it can adequately support high-resolution display panels. Thus, thepresent invention is friendly to both global environmental and spaceenvironment.

1. A drive method of an EL display apparatus that comprises a switchingelement which turns on and off a current path between a drivertransistor and an EL element, in each pixel, the drive methodcomprising: aggregating image data or data equivalent to image data; andturning off the switching element for a longer period if the aggregateddata is large in amount than if the aggregated data is small in amount.2. An EL display apparatus comprising: a display panel in which ELelements are formed in a matrix; and a source driver circuit configuredto supply programming current to the display panel, wherein the sourcedriver circuit comprises an output stage that has a plurality of unitcurrent elements and a variable circuit configured to control currentflowing from the unit current elements.
 3. A drive method of an ELdisplay apparatus that includes a moving-picture detection circuit thatdetects moving pictures and a feature extraction circuit that extractsfeatures of video images, the drive method of the EL display apparatuscomprising: first changing a number of selected pixel rows depending onoutput data from the moving-picture detection circuit; and secondchanging the number of selected pixel rows depending on output data fromthe feature extraction circuit.
 4. An EL display apparatus that controlsbrightness of a screen using a ratio between non-display and displayareas on the screen, the EL display apparatus comprising: a display areain which EL elements and driver transistors that drive the EL elementsare formed in a matrix; gate signal lines configured to transmitvoltages that turn on and off the EL elements in each pixel row; a gatedriver circuit configured to drive the gate signal lines; an aggregationcircuit configured to aggregate image data or data equivalent to imagedata; and a conversion circuit configured to convert aggregation resultsproduced by the aggregation circuit into a start pulse signal for thegate driver circuit.
 5. A control method of an EL display apparatus thatcontrols brightness of a screen using a ratio between non-display anddisplay areas on the screen, the control method comprising: generating adelay time when changing the ratio between the non-display and displayareas on the screen from a first ratio to a second ratio.
 6. The drivemethod of an EL display apparatus according to claim 5, wherein thedisplay area/(the non-display area+the display area on the screen) isfrom 1/16 to 1/1 both inclusive.
 7. An EL display apparatus comprising:a display panel in which each pixel contains a capacitor, an EL element,and a P-channel driver transistor configured to supply current to the ELelement, and wherein the pixels are arranged in a matrix; and a sourcedriver circuit configured to supply programming current to the displaypanel, wherein the source driver circuit comprises an output stage thathas an N-channel unit transistor configured to output a plurality ofunit currents.
 8. The EL display apparatus according to the claim 7,wherein a capacitance of a capacitor is Cs (pF) and one pixel occupiesan area of S (square μm), and a condition 500/S≦Cs≦20000/S is satisfied.9. The EL display apparatus according to claim 7, wherein a pixel sizeis A (square mm) and predetermined white raster display brightness is B(nt), and a programming current I (μA) from the source driver circuitsatisfies a condition (A×B)/20≦1≦(A×B).
 10. The EL display apparatusaccording to claim 7, wherein a number of gradations is K and a size ofthe unit transistor is St (square μm), and conditions 40≦K/{squareroot}{square root over ( )}(St) and St≦300 are satisfied.
 11. The ELdisplay apparatus according to claim 7, wherein a number of gradationsis K, channel length of the unit transistor is L (μm), and channel widthis W (μm), and a condition ({square root}{square root over ()}(K/16))≦L/W≦{square root}{square root over ( )}(K/16))×20 issatisfied.
 12. An EL display apparatus comprising: a first EL displaypanel including a first display screen; a second EL display panelincluding a second display screen; and a flexible board configured toconnect source signal lines of the first EL display panel with sourcesignal lines of the second EL display panel, wherein a channel width ofdriver transistors that drive pixels is W (μm) and a channel length is L(μm), and W/L differs between the driver transistor that drives pixelsin the first display screen and the driver transistor that drives pixelsin the second display screen.